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<title>rt-thread.git/components/drivers/core, branch master</title>
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<id>http://cgit.235523.xyz/rt-thread.git/atom/components/drivers/core?h=master</id>
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<updated>2026-10-19T10:49:16Z</updated>
<entry>
<title>[bsp][spacemit/k1] first version #11132</title>
<updated>2026-10-19T10:49:16Z</updated>
<author>
<name>GUI</name>
<email>39894654+GuEe-GUI@users.noreply.github.com</email>
</author>
<published>2026-10-19T10:49:16Z</published>
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<id>urn:sha1:1c801efabc36337d0013721eb30b11de0adb3075</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[ARCH/RISC-V] Next RISC-V (#10320)</title>
<updated>2026-10-17T01:44:26Z</updated>
<author>
<name>GUI</name>
<email>39894654+GuEe-GUI@users.noreply.github.com</email>
</author>
<published>2026-10-17T01:44:26Z</published>
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<id>urn:sha1:8d8dc96b67eee53af2841a8819364d52fbec39cb</id>
<content type='text'>
* [libcpu][risc-v] Refactor the RISC-V architecture port

Introduce an opt-in unified RISC-V common layer for RV32 and RV64 while keeping existing BSPs on the legacy implementation during migration.

- use ARCH_RISCV and ARCH_CPU_64BIT for architecture and XLEN selection
- unify context, trap, MMU, cache, timer, SBI, SMP and ISA handling
- add PLIC, CLIC, ACLINT, APLIC and IMSIC support
- map physical hart IDs to contiguous logical CPU IDs
- add T-Head vendor overrides while preserving legacy ports
- migrate qemu-virt64-riscv with RV32 and RV64 support
- update clock_time, MM, LWP, OFW, PCI and Rust integration

Existing BSPs continue using legacy_common or common64 unless they select RT_USING_RISCV_NEW_COMMON.

Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;

* [libcpu][risc-v] skip disabled CPU nodes in early FDT walk

Rbb666 noted that rt_hw_fdt_install_early() walked every /cpus child
without checking status, so disabled cores still joined hart registration
and MMU capability probing. Skip nodes that are not okay/ok via
rt_fdt_device_is_available() before reading reg or mmu-type.

Signed-off-by: seteiro &lt;chenmoushun@163.com&gt;

* [libcpu][risc-v] Fix per-CPU page table mapping

- reuse existing non-leaf page table entries when mapping per-CPU areas
- reject leaf entry conflicts instead of overwriting mappings

Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;

---------

Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;
Signed-off-by: seteiro &lt;chenmoushun@163.com&gt;
Co-authored-by: seteiro &lt;chenmoushun@163.com&gt;</content>
</entry>
<entry>
<title>fix(dm): route Cortex-M resets through power core</title>
<updated>2026-08-12T04:54:50Z</updated>
<author>
<name>Rbb666</name>
<email>zhangbingru@rt-thread.com</email>
</author>
<published>2026-08-03T03:54:06Z</published>
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<id>urn:sha1:1f23e3f27052a6b7fd75def2da634c79db5773e2</id>
<content type='text'>
</content>
</entry>
<entry>
<title>feat(dm): support OFW on Cortex-M targets</title>
<updated>2026-08-12T04:54:50Z</updated>
<author>
<name>Rbb666</name>
<email>zhangbingru@rt-thread.com</email>
</author>
<published>2026-07-31T07:07:36Z</published>
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<id>urn:sha1:6b4f34204ed2da80b7c37b912612c65cebc30ce3</id>
<content type='text'>
Add the ARM NVIC PIC driver, no-MMU I/O mapping, built-in FDT support, and Cortex-M CPU hooks required by the native RT-Thread device model.
</content>
</entry>
<entry>
<title>[dm][core] Add rt_bus_probe_device API</title>
<updated>2026-08-03T01:36:21Z</updated>
<author>
<name>GuEe-GUI</name>
<email>2991707448@qq.com</email>
</author>
<published>2026-08-01T14:12:19Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=fe751c152101fc88ad887b06d91e2d96aafc2883'/>
<id>urn:sha1:fe751c152101fc88ad887b06d91e2d96aafc2883</id>
<content type='text'>
Add rt_bus_probe_device() to retry driver matching for a registered
but unbound device. Use it when an OFW-created platform device
is requested again, while preserving native-bus ownership
for I2C, SPI, and other non-platform devices.
Also instantiate eligible child platform devices after a parent node is registered.

Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;
</content>
</entry>
<entry>
<title>[dm][pmdomain] fixup the child register layout</title>
<updated>2026-04-07T14:30:14Z</updated>
<author>
<name>GuEe-GUI</name>
<email>2991707448@qq.com</email>
</author>
<published>2026-04-07T05:51:34Z</published>
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<id>urn:sha1:0b317943264ef01f67c4990ca13b0d873a7517d3</id>
<content type='text'>
Link: https://github.com/RT-Thread/rt-thread/issues/11308

Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;
</content>
</entry>
<entry>
<title>[drivers] Fix OFW bus conflict and prevent duplicate device creation</title>
<updated>2026-01-20T14:05:28Z</updated>
<author>
<name>lhxj</name>
<email>2743257167@qq.com</email>
</author>
<published>2025-12-25T09:56:52Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=7641ef68855601bc73252546bf41a96d6078444e'/>
<id>urn:sha1:7641ef68855601bc73252546bf41a96d6078444e</id>
<content type='text'>
Problem:
When enumerating device tree nodes, platform bus and native buses (I2C/SPI)
may create duplicate devices for the same OFW node, causing cross-bus conflicts.
This triggers assertion failure '(dev-&gt;bus != new_bus)' in
rt_bus_reload_driver_device() during boot on minimal DM-enabled systems.

Root Cause:
1. Platform bus tries to reload devices that already belong to other buses
   by calling rt_bus_reload_driver_device(dev-&gt;bus, dev), which violates
   the API contract (requires dev-&gt;bus != new_bus).
2. Native buses (I2C/SPI) do not mark OFW nodes as occupied, so platform
   bus creates duplicate platform devices for I2C/SPI client nodes.

Solution:
1. components/drivers/core/platform_ofw.c: Return RT_EOK when np-&gt;dev exists,
   letting the native bus handle device lifecycle instead of cross-bus reload.
2. components/drivers/i2c/dev_i2c_bus.c: Mark i2c_client_np-&gt;dev during scan
   to prevent platform bus from duplicating I2C client devices.
3. components/drivers/spi/dev_spi_bus.c: Mark spi_dev_np-&gt;dev during scan
   to prevent platform bus from duplicating SPI devices.

Tested on Spacemit K1 RISC-V platform with minimal DM configuration.

Signed-off-by: lhxj &lt;2743257167@qq.com&gt;
</content>
</entry>
<entry>
<title>[dm][core] add common machine power interface</title>
<updated>2025-12-16T03:35:35Z</updated>
<author>
<name>GuEe-GUI</name>
<email>2991707448@qq.com</email>
</author>
<published>2025-12-12T17:21:48Z</published>
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<id>urn:sha1:491321140966e7acf8f9dd98a4536b4cc232b9f8</id>
<content type='text'>
Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;
</content>
</entry>
<entry>
<title>[dm][core] Update the OFW CLk init flow</title>
<updated>2025-12-13T08:35:32Z</updated>
<author>
<name>GuEe-GUI</name>
<email>2991707448@qq.com</email>
</author>
<published>2025-12-12T17:24:54Z</published>
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<id>urn:sha1:cbf3f8c3b4fbdd3391bf3c8d1300c7854729a1ca</id>
<content type='text'>
The clock should init before common platform devices.

Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;
</content>
</entry>
<entry>
<title>[dm][pinctrl] Set pinctrl default auto in platform bus. (#11052)</title>
<updated>2025-12-13T08:33:05Z</updated>
<author>
<name>GUI</name>
<email>39894654+GuEe-GUI@users.noreply.github.com</email>
</author>
<published>2025-12-13T08:33:05Z</published>
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<id>urn:sha1:1b4111a99e63cc731a51da9459e24b02692aa768</id>
<content type='text'>
Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;</content>
</entry>
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