rt-thread.git/components/drivers/include, branch copilot/fix-riscv-none-job-failure

[device][mmcsd] Fix Arm Compiler 5 build compatibility #11690

2026-09-07T03:18:41Z

[DM/OFW][PCI] Fix address translation and PCI resource enumeration (#11677)

2026-08-14T04:42:32Z

* [DM/OFW][PCI] Fix address translation and PCI resource enumeration Rework OFW address translation to walk nested bus ranges in the correct direction and cache "ranges" and "dma-ranges" independently. Handle PCI three-cell addresses without treating the PCI flags cell as part of the address, and fix CPU-to-DMA and DMA-to-CPU translation across nested buses. Fix PCI BAR sizing and assignment by disabling address decoding during probing, preserving BAR attribute bits, and programming 64-bit BARs correctly. Add device enable and disable helpers so resources and bus mastering are enabled before driver probe. Program bridge memory and prefetch windows while scanning downstream buses, correctly link child buses into the PCI bus hierarchy, and avoid unnecessary PCIe link retraining when the link is already active. Allow host bridges without a device-tree pci-domain property by allocating unique domains dynamically, while preserving explicit domain assignments. Fix MSI and MSI-X IRQ setup, rollback, vector addressing, and affinity selection. Add the Raspberry Pi PCI vendor ID for RP1 and other downstream devices. Signed-off-by: GuEe-GUI <2991707448@qq.com> * style: format code with clang-format * style: format complete changed files with clang-format * drivers: pci: address OFW review feedback * style: format PCI and OFW changes for current master --------- Signed-off-by: GuEe-GUI <2991707448@qq.com>

[dm][sdio] Update for SDHCI- #11684 #11684

2026-08-14T04:39:11Z

refactor(pic): dispatch NVIC IRQs through traps

2026-08-12T04:54:50Z

feat(dm): support OFW on Cortex-M targets

2026-08-12T04:54:50Z

Add the ARM NVIC PIC driver, no-MMU I/O mapping, built-in FDT support, and Cortex-M CPU hooks required by the native RT-Thread device model.

[dm][clk] fixup the work flow of CLK (#11673)

2026-08-08T10:25:02Z

* [dm][clk] fixup the work flow of CLK Add RT_CLK_F_SET_RATE_NO_REPARENT so clock providers can preserv the currently selected parent during rate changes. Round and re-read the effective clock rate after parent handling, skip redundant gate toggles and hardware programming when the target is already active, and fix error handling for parent-clock allocation failures. Signed-off-by: GuEe-GUI <2991707448@qq.com> * style: format code with clang-format * style: format complete changed files with clang-format --------- Signed-off-by: GuEe-GUI <2991707448@qq.com>

[dm][phye] Add Mode/State and MIPI D-PHY timing helper (#11675)

2026-08-07T13:31:43Z

* [dm][phye] Add Mode/State and MIPI D-PHY timing helper Extend the generic PHY framework with cached mode and submode state, avoiding redundant hardware mode changes. Add MIPI D-PHY default timing calculation helpers based on pixel clock or lane high-speed clock, and expose the new API through rtdevice.h. Signed-off-by: GuEe-GUI <2991707448@qq.com> * style: format code with clang-format * style: format complete changed files with clang-format --------- Signed-off-by: GuEe-GUI <2991707448@qq.com>

[dm][ufs] fixup the ufs supported (#11646)

2026-08-07T08:54:29Z

* [dm][block] add 4K support for EFI partion Signed-off-by: GuEe-GUI <2991707448@qq.com> * [dm][ufs] fixup the linkup flow Signed-off-by: GuEe-GUI <2991707448@qq.com> * style: format code with clang-format * style: format complete changed files with clang-format * drivers: address UFS review feedback --------- Signed-off-by: GuEe-GUI <2991707448@qq.com>

style: format code with clang-format

2026-08-07T01:26:42Z

[dm][graphic] update graphic

2026-08-07T01:26:42Z

1. Add FB_ACTIVATE_* cmd 2. Fixup the vsync 3. Update the graphic test Signed-off-by: GuEe-GUI <2991707448@qq.com>