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<title>rt-thread.git/components/drivers/mfd, branch master</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/rt-thread.git/atom/components/drivers/mfd?h=master</id>
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<updated>2026-10-17T01:44:26Z</updated>
<entry>
<title>[ARCH/RISC-V] Next RISC-V (#10320)</title>
<updated>2026-10-17T01:44:26Z</updated>
<author>
<name>GUI</name>
<email>39894654+GuEe-GUI@users.noreply.github.com</email>
</author>
<published>2026-10-17T01:44:26Z</published>
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<id>urn:sha1:8d8dc96b67eee53af2841a8819364d52fbec39cb</id>
<content type='text'>
* [libcpu][risc-v] Refactor the RISC-V architecture port

Introduce an opt-in unified RISC-V common layer for RV32 and RV64 while keeping existing BSPs on the legacy implementation during migration.

- use ARCH_RISCV and ARCH_CPU_64BIT for architecture and XLEN selection
- unify context, trap, MMU, cache, timer, SBI, SMP and ISA handling
- add PLIC, CLIC, ACLINT, APLIC and IMSIC support
- map physical hart IDs to contiguous logical CPU IDs
- add T-Head vendor overrides while preserving legacy ports
- migrate qemu-virt64-riscv with RV32 and RV64 support
- update clock_time, MM, LWP, OFW, PCI and Rust integration

Existing BSPs continue using legacy_common or common64 unless they select RT_USING_RISCV_NEW_COMMON.

Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;

* [libcpu][risc-v] skip disabled CPU nodes in early FDT walk

Rbb666 noted that rt_hw_fdt_install_early() walked every /cpus child
without checking status, so disabled cores still joined hart registration
and MMU capability probing. Skip nodes that are not okay/ok via
rt_fdt_device_is_available() before reading reg or mmu-type.

Signed-off-by: seteiro &lt;chenmoushun@163.com&gt;

* [libcpu][risc-v] Fix per-CPU page table mapping

- reuse existing non-leaf page table entries when mapping per-CPU areas
- reject leaf entry conflicts instead of overwriting mappings

Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;

---------

Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;
Signed-off-by: seteiro &lt;chenmoushun@163.com&gt;
Co-authored-by: seteiro &lt;chenmoushun@163.com&gt;</content>
</entry>
<entry>
<title>[DM/MFD] Add QEMU EDU for PCI study</title>
<updated>2025-12-07T14:58:09Z</updated>
<author>
<name>GuEe-GUI</name>
<email>2991707448@qq.com</email>
</author>
<published>2025-12-01T08:53:00Z</published>
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<id>urn:sha1:2995112bee0304edae5b6d0f097eacf97216e01c</id>
<content type='text'>
EDU Support DMA (lower 32 bits) and factorial, MSI-X, user can change device or driver
to study PCI.

Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;
</content>
</entry>
<entry>
<title>[DM/MFDD] Make Kconfig import for DM</title>
<updated>2025-12-07T14:58:09Z</updated>
<author>
<name>GuEe-GUI</name>
<email>2991707448@qq.com</email>
</author>
<published>2025-12-01T08:52:36Z</published>
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<id>urn:sha1:c9b8cb58979f342471c8f08ddc535eedfe684b96</id>
<content type='text'>
Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;
</content>
</entry>
<entry>
<title>[DM] Replace spinlock static init by RT_DEFINE_SPINLOCK</title>
<updated>2025-02-11T06:58:18Z</updated>
<author>
<name>GuEe-GUI</name>
<email>2991707448@qq.com</email>
</author>
<published>2025-02-10T06:19:30Z</published>
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<id>urn:sha1:f50607628192b7ad1828e811bba238993b9afd55</id>
<content type='text'>
Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;
</content>
</entry>
<entry>
<title>[DM/FEATURE] Support MFD syscon</title>
<updated>2024-11-20T07:53:23Z</updated>
<author>
<name>GuEe-GUI</name>
<email>2991707448@qq.com</email>
</author>
<published>2024-10-31T11:33:15Z</published>
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<id>urn:sha1:10cac76d3bfc86fda251013c5573c146836762e7</id>
<content type='text'>
MFD (Multifunction device) with System Controller Register Read/Write.

Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;
</content>
</entry>
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