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<title>rt-thread.git/components/drivers/ofw/fdt.c, branch master</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/rt-thread.git/atom/components/drivers/ofw/fdt.c?h=master</id>
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<updated>2026-10-17T01:44:26Z</updated>
<entry>
<title>[ARCH/RISC-V] Next RISC-V (#10320)</title>
<updated>2026-10-17T01:44:26Z</updated>
<author>
<name>GUI</name>
<email>39894654+GuEe-GUI@users.noreply.github.com</email>
</author>
<published>2026-10-17T01:44:26Z</published>
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<id>urn:sha1:8d8dc96b67eee53af2841a8819364d52fbec39cb</id>
<content type='text'>
* [libcpu][risc-v] Refactor the RISC-V architecture port

Introduce an opt-in unified RISC-V common layer for RV32 and RV64 while keeping existing BSPs on the legacy implementation during migration.

- use ARCH_RISCV and ARCH_CPU_64BIT for architecture and XLEN selection
- unify context, trap, MMU, cache, timer, SBI, SMP and ISA handling
- add PLIC, CLIC, ACLINT, APLIC and IMSIC support
- map physical hart IDs to contiguous logical CPU IDs
- add T-Head vendor overrides while preserving legacy ports
- migrate qemu-virt64-riscv with RV32 and RV64 support
- update clock_time, MM, LWP, OFW, PCI and Rust integration

Existing BSPs continue using legacy_common or common64 unless they select RT_USING_RISCV_NEW_COMMON.

Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;

* [libcpu][risc-v] skip disabled CPU nodes in early FDT walk

Rbb666 noted that rt_hw_fdt_install_early() walked every /cpus child
without checking status, so disabled cores still joined hart registration
and MMU capability probing. Skip nodes that are not okay/ok via
rt_fdt_device_is_available() before reading reg or mmu-type.

Signed-off-by: seteiro &lt;chenmoushun@163.com&gt;

* [libcpu][risc-v] Fix per-CPU page table mapping

- reuse existing non-leaf page table entries when mapping per-CPU areas
- reject leaf entry conflicts instead of overwriting mappings

Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;

---------

Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;
Signed-off-by: seteiro &lt;chenmoushun@163.com&gt;
Co-authored-by: seteiro &lt;chenmoushun@163.com&gt;</content>
</entry>
<entry>
<title>feat(dm): support OFW on Cortex-M targets</title>
<updated>2026-08-12T04:54:50Z</updated>
<author>
<name>Rbb666</name>
<email>zhangbingru@rt-thread.com</email>
</author>
<published>2026-07-31T07:07:36Z</published>
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<id>urn:sha1:6b4f34204ed2da80b7c37b912612c65cebc30ce3</id>
<content type='text'>
Add the ARM NVIC PIC driver, no-MMU I/O mapping, built-in FDT support, and Cortex-M CPU hooks required by the native RT-Thread device model.
</content>
</entry>
<entry>
<title>[drivers][ofw] Update OFW #11004</title>
<updated>2025-12-11T03:05:47Z</updated>
<author>
<name>GUI</name>
<email>39894654+GuEe-GUI@users.noreply.github.com</email>
</author>
<published>2025-12-11T03:05:47Z</published>
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<id>urn:sha1:f39a86266a66561d37be86b9666ec40af2355e6c</id>
<content type='text'>
Fixup fdt address reg and cells parse.
Support only option name way for earlycon.
Find the console device when using "stdout-path".</content>
</entry>
<entry>
<title>[DM/FDT] Fix garble when booting</title>
<updated>2025-04-14T10:04:39Z</updated>
<author>
<name>1078249029</name>
<email>1078249029@qq.com</email>
</author>
<published>2025-04-02T03:30:21Z</published>
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<id>urn:sha1:9d1fb86020c250da6248d8b942b553a0f84aeb6f</id>
<content type='text'>
Fix garble caused by empty implementation of earlycon series
function in driver.If driver doesn't offer earlycon_id or rt_f
dt_earlycon_id.setup function but open option, the checking
of best_earlycon_id will failed.

Signed-off-by: 1078249029 &lt;1078249029@qq.com&gt;
</content>
</entry>
<entry>
<title>[DM/FDT] Fixup earlycon loss old messages.</title>
<updated>2025-02-10T07:55:54Z</updated>
<author>
<name>GuEe-GUI</name>
<email>2991707448@qq.com</email>
</author>
<published>2025-01-18T03:57:39Z</published>
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<id>urn:sha1:12fded19f531a4711e36a19de1f1f5055c1be110</id>
<content type='text'>
The `rt_fdt_scan_chosen_stdout` will init fdt_earlycon data
without `msg` only, the `msg_idx` should not clean, too.
Because we check if have old messages by `msg_idx`

Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;
</content>
</entry>
<entry>
<title>[componets] fix when printf 0 addr by %p will return nil</title>
<updated>2024-12-10T00:45:40Z</updated>
<author>
<name>zhujiale</name>
<email>945386260@qq.com</email>
</author>
<published>2024-12-03T08:19:29Z</published>
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<id>urn:sha1:e7b30ed2ccf53c2da5128b33ab83ae0e3823fbff</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[DM/FDT] Fixup memory address reserved and translate in early</title>
<updated>2024-09-19T13:16:56Z</updated>
<author>
<name>GuEe-GUI</name>
<email>2991707448@qq.com</email>
</author>
<published>2024-06-04T07:46:24Z</published>
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<id>urn:sha1:87906499a387101e2f5b04f36fba8a3d21f25a8c</id>
<content type='text'>
1.Fixup `fdt_reserved_memory_reg` loop time.
2.Fixup `rt_fdt_translate_address` cells value reader.

Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;
</content>
</entry>
<entry>
<title>[FEATURE/FDT] Add bootargs select in early</title>
<updated>2024-09-13T21:33:29Z</updated>
<author>
<name>GuEe-GUI</name>
<email>2991707448@qq.com</email>
</author>
<published>2024-09-10T05:34:54Z</published>
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<id>urn:sha1:117e6ed347ee67699238170e76633d70703c2b55</id>
<content type='text'>
Maybe use for memory/DMA buffer init before
ofw_node unflatten.

Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;
</content>
</entry>
<entry>
<title>fix initrd scan err</title>
<updated>2024-07-03T16:34:01Z</updated>
<author>
<name>zhao maosheng</name>
<email>zmshahaha@gmail.com</email>
</author>
<published>2024-07-03T10:16:20Z</published>
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<id>urn:sha1:95aa97714b5c26c04f51d2eb7b6c74f8b98596f6</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[libcpu][aarch64]memory setup using memblock (#9092)</title>
<updated>2024-06-26T06:36:49Z</updated>
<author>
<name>zms123456</name>
<email>85141075+zmshahaha@users.noreply.github.com</email>
</author>
<published>2024-06-26T06:36:49Z</published>
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<id>urn:sha1:b785ef9ed76fcf97d3f2d59e02bfaa8b5f6cc74e</id>
<content type='text'>
* memory setup using memblock

* map pages later</content>
</entry>
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