rt-thread.git/components/drivers/ofw, branch v5.3.0

[DM/OFW][PCI] Fix address translation and PCI resource enumeration (#11677)

2026-08-14T04:42:32Z

* [DM/OFW][PCI] Fix address translation and PCI resource enumeration Rework OFW address translation to walk nested bus ranges in the correct direction and cache "ranges" and "dma-ranges" independently. Handle PCI three-cell addresses without treating the PCI flags cell as part of the address, and fix CPU-to-DMA and DMA-to-CPU translation across nested buses. Fix PCI BAR sizing and assignment by disabling address decoding during probing, preserving BAR attribute bits, and programming 64-bit BARs correctly. Add device enable and disable helpers so resources and bus mastering are enabled before driver probe. Program bridge memory and prefetch windows while scanning downstream buses, correctly link child buses into the PCI bus hierarchy, and avoid unnecessary PCIe link retraining when the link is already active. Allow host bridges without a device-tree pci-domain property by allocating unique domains dynamically, while preserving explicit domain assignments. Fix MSI and MSI-X IRQ setup, rollback, vector addressing, and affinity selection. Add the Raspberry Pi PCI vendor ID for RP1 and other downstream devices. Signed-off-by: GuEe-GUI <2991707448@qq.com> * style: format code with clang-format * style: format complete changed files with clang-format * drivers: pci: address OFW review feedback * style: format PCI and OFW changes for current master --------- Signed-off-by: GuEe-GUI <2991707448@qq.com>

feat(dm): support OFW on Cortex-M targets

2026-08-12T04:54:50Z

Add the ARM NVIC PIC driver, no-MMU I/O mapping, built-in FDT support, and Cortex-M CPU hooks required by the native RT-Thread device model.

[drivers][ofw] Update OFW #11004

2025-12-11T03:05:47Z

Fixup fdt address reg and cells parse. Support only option name way for earlycon. Find the console device when using "stdout-path".

[DM/FDT] Fix garble when booting

2025-04-14T10:04:39Z

Fix garble caused by empty implementation of earlycon series function in driver.If driver doesn't offer earlycon_id or rt_f dt_earlycon_id.setup function but open option, the checking of best_earlycon_id will failed. Signed-off-by: 1078249029 <1078249029@qq.com>

[DM/OFW] check available in stub probe

2025-03-05T01:41:49Z

device node should not probe in stub if device is not available.

[DM] Replace spinlock static init by RT_DEFINE_SPINLOCK

2025-02-11T06:58:18Z

Signed-off-by: GuEe-GUI <2991707448@qq.com>

[DM/FDT] Fixup earlycon loss old messages.

2025-02-10T07:55:54Z

The `rt_fdt_scan_chosen_stdout` will init fdt_earlycon data without `msg` only, the `msg_idx` should not clean, too. Because we check if have old messages by `msg_idx` Signed-off-by: GuEe-GUI <2991707448@qq.com>

[OFW] Delete redundant strcasecmp function

2024-12-14T17:40:39Z

[componets] fix when printf 0 addr by %p will return nil

2024-12-10T00:45:40Z

[DM/FEATURE] Support reset controller (#9630)

2024-11-26T02:02:50Z

* [DM/FEATURE] Support reset controller Reset controllers are central units that control the reset signals to multiple peripherals. The reset controller API is split into two parts: 1. The consumer driver interface, which allows peripheral drivers to request control over their reset input signals 2. The reset controller driver interface which is used by drivers for reset controller devices to register their reset controls to provide them to the consumers. * [RESET/SIMPLE] Support simple reset Currently this driver supports: - Altera SoCFPGAs - ASPEED BMC SoCs - Bitmain BM1880 SoC - Realtek SoCs - RCC reset controller in STM32 MCUs - Allwinner SoCs - SiFive FU740 SoCs - Sophgo SoCs Signed-off-by: GuEe-GUI <2991707448@qq.com>