rt-thread.git/components/drivers/pci/endpoint, branch master

drivers: pci: Fix endpoint MSI setup

2026-07-08T06:03:38Z

rt_pci_ep_set_msi() checked the set_msix callback before calling set_msi. That rejects endpoint controllers that implement MSI without MSI-X, and can call through a NULL set_msi pointer when only MSI-X is provided. The same helper converts a requested MSI vector count into the log2 field passed to the controller. Stop after the first value large enough for the request so smaller requests are not widened by later loop iterations. Generated-by: OpenAI Codex Signed-off-by: Old-Ding <35417409+Old-Ding@users.noreply.github.com>

[DM/PCI] Fixup the C99, 6.8.1 Labeled statements p4

2025-12-04T07:53:55Z

Signed-off-by: GuEe-GUI <2991707448@qq.com>

[DM] Replace spinlock static init by RT_DEFINE_SPINLOCK

2025-02-11T06:58:18Z

Signed-off-by: GuEe-GUI <2991707448@qq.com>

[DM/PCI] Add memory window pool for EP

2024-11-28T01:46:58Z

Signed-off-by: GuEe-GUI <2991707448@qq.com>

[DM/Feature] Basic PCI/PCIe (Peripheral Component Interconnect Express) bus

2024-09-06T21:45:03Z

PCI/PCIe have better performance and more devices support, such as NVMe, GPU, Powerful NIC (Like RDMA). PCI/PCIe can access control by IOMMU that the virtualiztion and userspace driver will more safety. PCI/PCIe device could hot plugging, no design modifications SoC required, PCI/PCIe on Embedded SoC is popular now. We make a simple framework to support them. Feature Lists: 1.PCI INTx: the INT[A-D] pin IRQ for legacy PCI, work with platform PIC. 2.MSI/MSI-X: the message write IRQ for PCIe, work with platform's PIC. 3.PME: we only support the D0, D1, D2, D3HOT, D3COLD init by framework. 4.Endpoint: a simple EP framework for PCI FPGA or NTB function. 5.OFW: we only support work on OFW SoC, ACPI support in the future maybe. Host controller: 1. Common PCI host controller on ECAM. 2. Generic PCI host controller on ECAM. Signed-off-by: GuEe-GUI <2991707448@qq.com>