rt-thread.git/components/drivers/pci/endpoint, branch v5.2.2Unnamed repository; edit this file 'description' to name the repository.http://cgit.235523.xyz/rt-thread.git/atom/components/drivers/pci/endpoint?h=v5.2.22025-02-11T06:58:18Z[DM] Replace spinlock static init by RT_DEFINE_SPINLOCK2025-02-11T06:58:18ZGuEe-GUI2991707448@qq.com2025-02-10T06:19:30Zurn:sha1:f50607628192b7ad1828e811bba238993b9afd55
Signed-off-by: GuEe-GUI <2991707448@qq.com>
[DM/PCI] Add memory window pool for EP2024-11-28T01:46:58ZGuEe-GUI2991707448@qq.com2024-11-27T09:13:27Zurn:sha1:50982cd970fc5b70830be0cb7c71b1bc50fca5b0
Signed-off-by: GuEe-GUI <2991707448@qq.com>
[DM/Feature] Basic PCI/PCIe (Peripheral Component Interconnect Express) bus2024-09-06T21:45:03ZGuEe-GUI2991707448@qq.com2024-05-30T09:47:56Zurn:sha1:2168ed8e7d408aeada3427ebbb90bb8996885668
PCI/PCIe have better performance and more devices support, such as
NVMe, GPU, Powerful NIC (Like RDMA). PCI/PCIe can access control by
IOMMU that the virtualiztion and userspace driver will more safety.
PCI/PCIe device could hot plugging, no design modifications SoC required,
PCI/PCIe on Embedded SoC is popular now.
We make a simple framework to support them.
Feature Lists:
1.PCI INTx: the INT[A-D] pin IRQ for legacy PCI, work with platform PIC.
2.MSI/MSI-X: the message write IRQ for PCIe, work with platform's PIC.
3.PME: we only support the D0, D1, D2, D3HOT, D3COLD init by framework.
4.Endpoint: a simple EP framework for PCI FPGA or NTB function.
5.OFW: we only support work on OFW SoC, ACPI support in the future maybe.
Host controller:
1. Common PCI host controller on ECAM.
2. Generic PCI host controller on ECAM.
Signed-off-by: GuEe-GUI <2991707448@qq.com>