rt-thread.git/components/drivers/pci/msi, branch copilot/fix-format-string-injection

[DM/PCI] Fixup the MSI info shuold free

2025-08-25T03:12:02Z

Signed-off-by: GuEe-GUI <2991707448@qq.com>

[DM] Replace spinlock static init by RT_DEFINE_SPINLOCK

2025-02-11T06:58:18Z

Signed-off-by: GuEe-GUI <2991707448@qq.com>

[DM/FIXUP] Fixup MSI first IRQ read offset

2024-11-20T08:34:10Z

Signed-off-by: GuEe-GUI <2991707448@qq.com>

[DM/FIXUP] Fixup PCI MSI global irq map

2024-11-20T08:34:10Z

Don't use `irq` as a var when clear MSI global irq map, the irq which alloc before will rewrite. Signed-off-by: GuEe-GUI <2991707448@qq.com>

[DM/Feature] Basic PCI/PCIe (Peripheral Component Interconnect Express) bus

2024-09-06T21:45:03Z

PCI/PCIe have better performance and more devices support, such as NVMe, GPU, Powerful NIC (Like RDMA). PCI/PCIe can access control by IOMMU that the virtualiztion and userspace driver will more safety. PCI/PCIe device could hot plugging, no design modifications SoC required, PCI/PCIe on Embedded SoC is popular now. We make a simple framework to support them. Feature Lists: 1.PCI INTx: the INT[A-D] pin IRQ for legacy PCI, work with platform PIC. 2.MSI/MSI-X: the message write IRQ for PCIe, work with platform's PIC. 3.PME: we only support the D0, D1, D2, D3HOT, D3COLD init by framework. 4.Endpoint: a simple EP framework for PCI FPGA or NTB function. 5.OFW: we only support work on OFW SoC, ACPI support in the future maybe. Host controller: 1. Common PCI host controller on ECAM. 2. Generic PCI host controller on ECAM. Signed-off-by: GuEe-GUI <2991707448@qq.com>