<feed xmlns='http://www.w3.org/2005/Atom'>
<title>rt-thread.git/components/drivers/pci, branch copilot/fix-riscv-none-job-failure</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/rt-thread.git/atom/components/drivers/pci?h=copilot%2Ffix-riscv-none-job-failure</id>
<link rel='self' href='http://cgit.235523.xyz/rt-thread.git/atom/components/drivers/pci?h=copilot%2Ffix-riscv-none-job-failure'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/'/>
<updated>2026-08-14T04:42:32Z</updated>
<entry>
<title>[DM/OFW][PCI] Fix address translation and PCI resource enumeration (#11677)</title>
<updated>2026-08-14T04:42:32Z</updated>
<author>
<name>GUI</name>
<email>39894654+GuEe-GUI@users.noreply.github.com</email>
</author>
<published>2026-08-14T04:42:32Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=7bf01ae18d33fee5971c499466e178b6b262a46b'/>
<id>urn:sha1:7bf01ae18d33fee5971c499466e178b6b262a46b</id>
<content type='text'>
* [DM/OFW][PCI] Fix address translation and PCI resource enumeration

Rework OFW address translation to walk nested bus ranges in the correct
direction and cache "ranges" and "dma-ranges" independently. Handle PCI
three-cell addresses without treating the PCI flags cell as part of the
address, and fix CPU-to-DMA and DMA-to-CPU translation across nested
buses.

Fix PCI BAR sizing and assignment by disabling address decoding during
probing, preserving BAR attribute bits, and programming 64-bit BARs
correctly. Add device enable and disable helpers so resources and bus
mastering are enabled before driver probe.

Program bridge memory and prefetch windows while scanning downstream
buses, correctly link child buses into the PCI bus hierarchy, and avoid
unnecessary PCIe link retraining when the link is already active.

Allow host bridges without a device-tree pci-domain property by
allocating unique domains dynamically, while preserving explicit domain
assignments.

Fix MSI and MSI-X IRQ setup, rollback, vector addressing, and affinity
selection.

Add the Raspberry Pi PCI vendor ID for RP1 and other downstream devices.

Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;

* style: format code with clang-format

* style: format complete changed files with clang-format

* drivers: pci: address OFW review feedback

* style: format PCI and OFW changes for current master

---------

Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;</content>
</entry>
<entry>
<title>drivers: pci: Fix endpoint MSI setup</title>
<updated>2026-07-08T06:03:38Z</updated>
<author>
<name>Old-Ding</name>
<email>35417409+Old-Ding@users.noreply.github.com</email>
</author>
<published>2026-07-05T20:30:13Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=c7f21bddeb25a37d03193054592a083e73bba37b'/>
<id>urn:sha1:c7f21bddeb25a37d03193054592a083e73bba37b</id>
<content type='text'>
rt_pci_ep_set_msi() checked the set_msix callback before calling set_msi. That rejects endpoint controllers that implement MSI without MSI-X, and can call through a NULL set_msi pointer when only MSI-X is provided.

The same helper converts a requested MSI vector count into the log2 field passed to the controller. Stop after the first value large enough for the request so smaller requests are not widened by later loop iterations.

Generated-by: OpenAI Codex
Signed-off-by: Old-Ding &lt;35417409+Old-Ding@users.noreply.github.com&gt;
</content>
</entry>
<entry>
<title>[dm][pci] fixup the shift of class in probe</title>
<updated>2026-03-02T01:37:07Z</updated>
<author>
<name>GuEe-GUI</name>
<email>2991707448@qq.com</email>
</author>
<published>2026-03-01T04:07:34Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=566e74af833fc5a734c18fc69fe105b8849d571a'/>
<id>urn:sha1:566e74af833fc5a734c18fc69fe105b8849d571a</id>
<content type='text'>
Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;
</content>
</entry>
<entry>
<title>[DM/PCI] Fixup the C99, 6.8.1 Labeled statements p4</title>
<updated>2025-12-04T07:53:55Z</updated>
<author>
<name>GuEe-GUI</name>
<email>2991707448@qq.com</email>
</author>
<published>2025-12-01T08:33:10Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=4337d7fb30905601ce3d3c2a73b79976b6dcbbdd'/>
<id>urn:sha1:4337d7fb30905601ce3d3c2a73b79976b6dcbbdd</id>
<content type='text'>
Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;
</content>
</entry>
<entry>
<title>[DM/PCI] Add SoC PCI Kconfig import</title>
<updated>2025-08-25T03:12:02Z</updated>
<author>
<name>GuEe-GUI</name>
<email>2991707448@qq.com</email>
</author>
<published>2025-08-20T08:39:15Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=af2c8ae1745f2231f04f94b65d4c41bee6b393c7'/>
<id>urn:sha1:af2c8ae1745f2231f04f94b65d4c41bee6b393c7</id>
<content type='text'>
Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;
</content>
</entry>
<entry>
<title>[DM/PCI] Fixup the DWC PCI resource release</title>
<updated>2025-08-25T03:12:02Z</updated>
<author>
<name>GuEe-GUI</name>
<email>2991707448@qq.com</email>
</author>
<published>2025-08-20T08:38:24Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=7d96990effb625e3ee1b7e6766495e4e8abbb9fc'/>
<id>urn:sha1:7d96990effb625e3ee1b7e6766495e4e8abbb9fc</id>
<content type='text'>
Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;
</content>
</entry>
<entry>
<title>[DM/PCI] Fixup the bus-range probe</title>
<updated>2025-08-25T03:12:02Z</updated>
<author>
<name>GuEe-GUI</name>
<email>2991707448@qq.com</email>
</author>
<published>2025-08-20T08:37:16Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=77e845e018a83a757f67ee0a05b090fef7aebcac'/>
<id>urn:sha1:77e845e018a83a757f67ee0a05b090fef7aebcac</id>
<content type='text'>
Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;
</content>
</entry>
<entry>
<title>[DM/PCI] Fixup the MSI info shuold free</title>
<updated>2025-08-25T03:12:02Z</updated>
<author>
<name>GuEe-GUI</name>
<email>2991707448@qq.com</email>
</author>
<published>2025-08-20T08:36:12Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=8731289055d30468f09d4106376963b9d9912e36'/>
<id>urn:sha1:8731289055d30468f09d4106376963b9d9912e36</id>
<content type='text'>
Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;
</content>
</entry>
<entry>
<title>[DM/PCI] Add /proc access in RT-Smart user.</title>
<updated>2025-05-23T05:22:25Z</updated>
<author>
<name>GuEe-GUI</name>
<email>2991707448@qq.com</email>
</author>
<published>2025-04-17T06:32:07Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=99fc1bb72b81b8da744ef8eb89d6a9e1d28716ce'/>
<id>urn:sha1:99fc1bb72b81b8da744ef8eb89d6a9e1d28716ce</id>
<content type='text'>
1. Add ROM base info.
2. Save th PM status.

Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;
</content>
</entry>
<entry>
<title>[DM] Replace spinlock static init by RT_DEFINE_SPINLOCK</title>
<updated>2025-02-11T06:58:18Z</updated>
<author>
<name>GuEe-GUI</name>
<email>2991707448@qq.com</email>
</author>
<published>2025-02-10T06:19:30Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=f50607628192b7ad1828e811bba238993b9afd55'/>
<id>urn:sha1:f50607628192b7ad1828e811bba238993b9afd55</id>
<content type='text'>
Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;
</content>
</entry>
</feed>
