rt-thread.git/components/drivers/pci, branch v5.2.0-beta

[DM] Replace spinlock static init by RT_DEFINE_SPINLOCK

2025-02-11T06:58:18Z

Signed-off-by: GuEe-GUI <2991707448@qq.com>

[DM/FIXUP] Fixup PCI build

2024-12-13T02:39:20Z

1. Add PCI include in rtdevice.h 2. Fixup `RT_KEY_ENABLED` loss. 3. remove waring type of `dw_pcie_ep_get_func_from_ep` return. Signed-off-by: GuEe-GUI <2991707448@qq.com>

[DM/PCI] Add DesignWare PCIe RC/EP base drivers

2024-11-28T01:46:58Z

Too many PCI controllers base on DesignWare PCIe. This is a modules. Signed-off-by: GuEe-GUI <2991707448@qq.com>

[DM/PCI] Add memory window pool for EP

2024-11-28T01:46:58Z

Signed-off-by: GuEe-GUI <2991707448@qq.com>

[DM/FIXUP] Add ms sleep for link status change

2024-11-26T03:14:51Z

We should wait a while for success or failure after link status change or will communicate fail with the endpoint. Signed-off-by: GuEe-GUI <2991707448@qq.com>

[DM/FIXUP] Fixup PCI device ofw private node for MSI

2024-11-26T03:14:51Z

Some PCI device devicetree is like: ```dts pcie@fe270000 { device_type = "pci"; msi-map = <0x1000 0x9c 0x1000 0x1000>; pcie@10 { reg = <0x100000 0x00 0x00 0x00 0x00>; #address-cells = <0x03>; #size-cells = <0x02>; pcie@10,0 { reg = <0x00 0x00 0x00 0x00 0x00>; }; }; }; ``` that the pcie@10,0 have a private ofw node, it will find property name `msi-map` or `msi-parent` fail. We should only find the property in host bridge's ofw node. Signed-off-by: GuEe-GUI <2991707448@qq.com>

[DM/FIXUP] Fixup MSI first IRQ read offset

2024-11-20T08:34:10Z

Signed-off-by: GuEe-GUI <2991707448@qq.com>

[DM/FIXUP] Fixup PCI MSI global irq map

2024-11-20T08:34:10Z

Don't use `irq` as a var when clear MSI global irq map, the irq which alloc before will rewrite. Signed-off-by: GuEe-GUI <2991707448@qq.com>

[feat] add pci api,the pci/pcie driver

2024-10-05T06:30:52Z

add pci api,the pci/pcie driver writer can use this to get resource of current device with flag,there are three flag : 1. PCI_BUS_REGION_F_MEM it mean memory space 2. PCI_BUS_REGION_F_IO it mean io space 3. PCI_BUS_REGION_F_PREFETCH it mean prefetchable memory

[DM/Feature] Basic PCI/PCIe (Peripheral Component Interconnect Express) bus

2024-09-06T21:45:03Z

PCI/PCIe have better performance and more devices support, such as NVMe, GPU, Powerful NIC (Like RDMA). PCI/PCIe can access control by IOMMU that the virtualiztion and userspace driver will more safety. PCI/PCIe device could hot plugging, no design modifications SoC required, PCI/PCIe on Embedded SoC is popular now. We make a simple framework to support them. Feature Lists: 1.PCI INTx: the INT[A-D] pin IRQ for legacy PCI, work with platform PIC. 2.MSI/MSI-X: the message write IRQ for PCIe, work with platform's PIC. 3.PME: we only support the D0, D1, D2, D3HOT, D3COLD init by framework. 4.Endpoint: a simple EP framework for PCI FPGA or NTB function. 5.OFW: we only support work on OFW SoC, ACPI support in the future maybe. Host controller: 1. Common PCI host controller on ECAM. 2. Generic PCI host controller on ECAM. Signed-off-by: GuEe-GUI <2991707448@qq.com>