rt-thread.git/components/drivers/pci, branch v5.2.1Unnamed repository; edit this file 'description' to name the repository.http://cgit.235523.xyz/rt-thread.git/atom/components/drivers/pci?h=v5.2.12025-05-23T05:22:25Z[DM/PCI] Add /proc access in RT-Smart user.2025-05-23T05:22:25ZGuEe-GUI2991707448@qq.com2025-04-17T06:32:07Zurn:sha1:99fc1bb72b81b8da744ef8eb89d6a9e1d28716ce
1. Add ROM base info.
2. Save th PM status.
Signed-off-by: GuEe-GUI <2991707448@qq.com>
[DM] Replace spinlock static init by RT_DEFINE_SPINLOCK2025-02-11T06:58:18ZGuEe-GUI2991707448@qq.com2025-02-10T06:19:30Zurn:sha1:f50607628192b7ad1828e811bba238993b9afd55
Signed-off-by: GuEe-GUI <2991707448@qq.com>
[DM/FIXUP] Fixup PCI build2024-12-13T02:39:20ZGuEe-GUI2991707448@qq.com2024-12-11T11:28:20Zurn:sha1:d248a3a2887dc4ec56c5d9cf8ffa535665f42eeb
1. Add PCI include in rtdevice.h
2. Fixup `RT_KEY_ENABLED` loss.
3. remove waring type of `dw_pcie_ep_get_func_from_ep` return.
Signed-off-by: GuEe-GUI <2991707448@qq.com>
[DM/PCI] Add DesignWare PCIe RC/EP base drivers2024-11-28T01:46:58ZGuEe-GUI2991707448@qq.com2024-11-27T03:29:48Zurn:sha1:88b8310d163c192ae2cfed4ca4b6260a027a889a
Too many PCI controllers base on DesignWare PCIe.
This is a modules.
Signed-off-by: GuEe-GUI <2991707448@qq.com>
[DM/PCI] Add memory window pool for EP2024-11-28T01:46:58ZGuEe-GUI2991707448@qq.com2024-11-27T09:13:27Zurn:sha1:50982cd970fc5b70830be0cb7c71b1bc50fca5b0
Signed-off-by: GuEe-GUI <2991707448@qq.com>
[DM/FIXUP] Add ms sleep for link status change2024-11-26T03:14:51ZGuEe-GUI2991707448@qq.com2024-11-25T12:42:08Zurn:sha1:71520fa9f1b769fa838e39ea5f00175424154376
We should wait a while for success or failure
after link status change or will communicate
fail with the endpoint.
Signed-off-by: GuEe-GUI <2991707448@qq.com>
[DM/FIXUP] Fixup PCI device ofw private node for MSI2024-11-26T03:14:51ZGuEe-GUI2991707448@qq.com2024-11-07T05:52:55Zurn:sha1:1ac80442947e975cbb338c942eb6127bd5464fc1
Some PCI device devicetree is like:
```dts
pcie@fe270000 {
device_type = "pci";
msi-map = <0x1000 0x9c 0x1000 0x1000>;
pcie@10 {
reg = <0x100000 0x00 0x00 0x00 0x00>;
#address-cells = <0x03>;
#size-cells = <0x02>;
pcie@10,0 {
reg = <0x00 0x00 0x00 0x00 0x00>;
};
};
};
```
that the pcie@10,0 have a private ofw node, it will find
property name `msi-map` or `msi-parent` fail.
We should only find the property in host bridge's ofw node.
Signed-off-by: GuEe-GUI <2991707448@qq.com>
[DM/FIXUP] Fixup MSI first IRQ read offset2024-11-20T08:34:10ZGuEe-GUI2991707448@qq.com2024-11-18T11:42:14Zurn:sha1:86ba3b666f2b9be4a50ac874d4732f45e06e5e9f
Signed-off-by: GuEe-GUI <2991707448@qq.com>
[DM/FIXUP] Fixup PCI MSI global irq map2024-11-20T08:34:10ZGuEe-GUI2991707448@qq.com2024-11-18T09:46:18Zurn:sha1:34cf382c8bce3b0e9799c9f881cd6df35075854e
Don't use `irq` as a var when clear MSI global
irq map, the irq which alloc before will rewrite.
Signed-off-by: GuEe-GUI <2991707448@qq.com>
[feat] add pci api,the pci/pcie driver2024-10-05T06:30:52Zzhuzhuzhu945386260@qq.com2024-10-05T06:30:52Zurn:sha1:ef426851ea3cc4aaf2beda8862cc0e0953cf4b6c
add pci api,the pci/pcie driver writer can use this to get resource of current device with flag,there are three flag :
1. PCI_BUS_REGION_F_MEM it mean memory space
2. PCI_BUS_REGION_F_IO it mean io space
3. PCI_BUS_REGION_F_PREFETCH it mean prefetchable memory