rt-thread.git/components/drivers/pin, branch v5.3.0-beta

feat(dm): support OFW on Cortex-M targets

2026-08-12T04:54:50Z

Add the ARM NVIC PIC driver, no-MMU I/O mapping, built-in FDT support, and Cortex-M CPU hooks required by the native RT-Thread device model.

[utest][pin] add pin loopback utest (#11445)

2026-06-22T08:03:58Z

* [utest][pin] add pin loopback utest * [utest][pin] add BSP CI coverage * [utest][pin] fix BSP CI config * [utest][pin] fix ra8p1 utest link section

[dm][pin][pinctrl] add new driver

2025-12-10T08:53:09Z

1. ARM PL061 GPIO 2. Single Pinctrl Signed-off-by: GuEe-GUI <2991707448@qq.com>

[dm][pin] fixup the DM Kconfig import in DM mode only

2025-12-10T08:53:09Z

Signed-off-by: GuEe-GUI <2991707448@qq.com>

[dm][pinctrl] new interface for 'pin_gpio_request'

2025-12-10T08:53:09Z

Some GPIO should apply GPIO mode by pinctrl, add `pin_ctrl_gpio_request` for GPIO driver to apply it auto. Signed-off-by: GuEe-GUI <2991707448@qq.com>

[DM] Replace spinlock static init by RT_DEFINE_SPINLOCK

2025-02-11T06:58:18Z

Signed-off-by: GuEe-GUI <2991707448@qq.com>

[DM/FEATURE] Support import SoC PIN config

2024-12-02T13:15:17Z

Signed-off-by: GuEe-GUI <2991707448@qq.com>

[DM/FEATURE] Support virtual pin

2024-12-02T13:15:17Z

1. There is only one GPIO device in System. 2. For Pin API input is pin number 3. Add sets pin debounce time API. So we need a virtual pin for multi gpio chip. Signed-off-by: GuEe-GUI <2991707448@qq.com>

[DM/FIXUP] Fixup pin propname check

2024-12-02T13:15:17Z

Signed-off-by: GuEe-GUI <2991707448@qq.com>

[DM/FIXUP] Fixup pin flags get from OFW

2024-12-02T13:15:17Z

Only check HIGH or LOW Signed-off-by: GuEe-GUI <2991707448@qq.com>