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<title>rt-thread.git/components/lwp/arch/risc-v/rv64/lwp_gcc.S, branch master</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/rt-thread.git/atom/components/lwp/arch/risc-v/rv64/lwp_gcc.S?h=master</id>
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<updated>2026-10-17T01:44:26Z</updated>
<entry>
<title>[ARCH/RISC-V] Next RISC-V (#10320)</title>
<updated>2026-10-17T01:44:26Z</updated>
<author>
<name>GUI</name>
<email>39894654+GuEe-GUI@users.noreply.github.com</email>
</author>
<published>2026-10-17T01:44:26Z</published>
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<id>urn:sha1:8d8dc96b67eee53af2841a8819364d52fbec39cb</id>
<content type='text'>
* [libcpu][risc-v] Refactor the RISC-V architecture port

Introduce an opt-in unified RISC-V common layer for RV32 and RV64 while keeping existing BSPs on the legacy implementation during migration.

- use ARCH_RISCV and ARCH_CPU_64BIT for architecture and XLEN selection
- unify context, trap, MMU, cache, timer, SBI, SMP and ISA handling
- add PLIC, CLIC, ACLINT, APLIC and IMSIC support
- map physical hart IDs to contiguous logical CPU IDs
- add T-Head vendor overrides while preserving legacy ports
- migrate qemu-virt64-riscv with RV32 and RV64 support
- update clock_time, MM, LWP, OFW, PCI and Rust integration

Existing BSPs continue using legacy_common or common64 unless they select RT_USING_RISCV_NEW_COMMON.

Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;

* [libcpu][risc-v] skip disabled CPU nodes in early FDT walk

Rbb666 noted that rt_hw_fdt_install_early() walked every /cpus child
without checking status, so disabled cores still joined hart registration
and MMU capability probing. Skip nodes that are not okay/ok via
rt_fdt_device_is_available() before reading reg or mmu-type.

Signed-off-by: seteiro &lt;chenmoushun@163.com&gt;

* [libcpu][risc-v] Fix per-CPU page table mapping

- reuse existing non-leaf page table entries when mapping per-CPU areas
- reject leaf entry conflicts instead of overwriting mappings

Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;

---------

Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;
Signed-off-by: seteiro &lt;chenmoushun@163.com&gt;
Co-authored-by: seteiro &lt;chenmoushun@163.com&gt;</content>
</entry>
<entry>
<title>[lwp][rv64] riscv: fix potential signal handler infinite loop</title>
<updated>2025-07-23T01:39:17Z</updated>
<author>
<name>Yulong Wang</name>
<email>2302147681@qq.com</email>
</author>
<published>2025-07-13T04:04:20Z</published>
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<id>urn:sha1:ee1fe2024e5a6c0d8582a5225a3e1083b88b2032</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[lwp][rv64] restore tp register in arch_thread_signal_enter to fix user-mode memory access</title>
<updated>2025-07-23T01:38:35Z</updated>
<author>
<name>Yulong Wang</name>
<email>2302147681@qq.com</email>
</author>
<published>2025-07-12T13:10:48Z</published>
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<id>urn:sha1:e7a40ae6ec1fdcb0d74a4902cfbd50aee7ee8e8f</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[rv]修正signal退出后用户态sp少8的问题 (#9080)</title>
<updated>2024-06-24T13:36:32Z</updated>
<author>
<name>heyuanjie87</name>
<email>943313837@qq.com</email>
</author>
<published>2024-06-24T13:36:32Z</published>
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<id>urn:sha1:a5a89c439f905f68fee98f7b329b348a1c2171b3</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[rv]信号处理进入用户态前恢复gp (#9072)</title>
<updated>2024-06-21T01:09:41Z</updated>
<author>
<name>heyuanjie87</name>
<email>sc943313837@gmail.com</email>
</author>
<published>2024-06-21T01:09:41Z</published>
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<id>urn:sha1:06ad67d549533e11fd3a2488ee776e36441a4d27</id>
<content type='text'>
* [rv/virt/stackframe.h]添加GP寄存器保存偏移量宏

* 【rv/c906/stackframe.h]定义GP寄存器存储偏移量

* [rv]信号处理切换到用户态前恢复gp</content>
</entry>
<entry>
<title>[lwp/riscv]进入libc前初始化用户态sp (#8997)</title>
<updated>2024-05-28T22:52:38Z</updated>
<author>
<name>heyuanjie87</name>
<email>sc943313837@gmail.com</email>
</author>
<published>2024-05-28T22:52:38Z</published>
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<id>urn:sha1:326150e2f4991679f5a4e39cfdc42378a328e983</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[libcpu] discard rt_current_thread (#8976)</title>
<updated>2024-05-26T14:00:17Z</updated>
<author>
<name>Shell</name>
<email>smokewood@qq.com</email>
</author>
<published>2024-05-26T14:00:17Z</published>
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<id>urn:sha1:397cdcd1320d096d41523cbbe0bf743e872d5e70</id>
<content type='text'>
* [libcpu] rv64: discard rt_current_thread

* arm: using rt_thread_self to fetch current TCB</content>
</entry>
<entry>
<title>[component/lwp] support more feature of signal from IEEE Std 1003.1-2017 (#7828)</title>
<updated>2023-07-19T16:02:41Z</updated>
<author>
<name>Shell</name>
<email>smokewood@qq.com</email>
</author>
<published>2023-07-19T16:02:41Z</published>
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<id>urn:sha1:58e0ddf2879032495a74897c34e3605de929f82c</id>
<content type='text'>
Signed-off-by: Shell &lt;smokewood@qq.com&gt;</content>
</entry>
<entry>
<title>[libcpu][component][debug] add debug info for gdb (#7033)</title>
<updated>2023-05-14T15:48:16Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-05-14T15:48:16Z</published>
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<id>urn:sha1:b7554a70d21582cab97028477941fb692ef248b8</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[rt-smart] handling kernel from accessing unmapped user stack (#6957)</title>
<updated>2023-02-24T06:52:16Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-02-24T06:52:16Z</published>
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<id>urn:sha1:382e9bcac746b408b5b01ea2f59338428ab203dd</id>
<content type='text'>
[rt-smart] handling kernel from accessing unmapped user stack</content>
</entry>
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