rt-thread.git/components/lwp/arch/risc-v, branch master

[ARCH/RISC-V] Next RISC-V (#10320)

2026-10-17T01:44:26Z

* [libcpu][risc-v] Refactor the RISC-V architecture port Introduce an opt-in unified RISC-V common layer for RV32 and RV64 while keeping existing BSPs on the legacy implementation during migration. - use ARCH_RISCV and ARCH_CPU_64BIT for architecture and XLEN selection - unify context, trap, MMU, cache, timer, SBI, SMP and ISA handling - add PLIC, CLIC, ACLINT, APLIC and IMSIC support - map physical hart IDs to contiguous logical CPU IDs - add T-Head vendor overrides while preserving legacy ports - migrate qemu-virt64-riscv with RV32 and RV64 support - update clock_time, MM, LWP, OFW, PCI and Rust integration Existing BSPs continue using legacy_common or common64 unless they select RT_USING_RISCV_NEW_COMMON. Signed-off-by: GuEe-GUI <2991707448@qq.com> * [libcpu][risc-v] skip disabled CPU nodes in early FDT walk Rbb666 noted that rt_hw_fdt_install_early() walked every /cpus child without checking status, so disabled cores still joined hart registration and MMU capability probing. Skip nodes that are not okay/ok via rt_fdt_device_is_available() before reading reg or mmu-type. Signed-off-by: seteiro * [libcpu][risc-v] Fix per-CPU page table mapping - reuse existing non-leaf page table entries when mapping per-CPU areas - reject leaf entry conflicts instead of overwriting mappings Signed-off-by: GuEe-GUI <2991707448@qq.com> --------- Signed-off-by: GuEe-GUI <2991707448@qq.com> Signed-off-by: seteiro Co-authored-by: seteiro

更新 vdso 框架

2026-04-29T22:19:58Z

[components][clock_time] Refactor time subsystem around clock_time (#11111)

2026-01-31T09:44:27Z

* [components][clock_time] Refactor time subsystem around clock_time Introduce the clock_time core with clock source/event separation, high-resolution scheduling, and boot-time helpers, plus clock_timer adapters for timer peripherals. Remove legacy ktime/cputime/hwtimer implementations and migrate arch and BSP time paths to the new subsystem while keeping POSIX time integration functional. Update drivers, Kconfig/SConscript wiring, documentation, and tests; add clock_time overview docs and align naming to clock_boottime/clock_hrtimer/clock_timer. * [components][clock_time] Use BSP-provided clock timer frequency on riscv64 * [risc-v] Use runtime clock timer frequency for tick and delays * [bsp] Add clock timer frequency hooks for riscv64 boards * [bsp] Update Renesas RA driver doc clock_timer link * [bsp] Sync zynqmp-r5-axu4ev rtconfig after config refresh * [bsp][rk3500] Update rk3500 clock configuration * [bsp][hpmicro] Add rt_hw_us_delay hook and update board delays * [bsp][stm32l496-st-nucleo] enable clock_time for hwtimer sample in ci * [bsp][hpmicro] Fix rtconfig include scope for hpm6750evk Move rtconfig.h include outside the ENET_MULTIPLE_PORT guard for hpm6750evk and hpm6750evk2 so configuration macros are available regardless of ENET settings. * [bsp][raspi3] select clock time for systimer * [bsp][hpm5300evk] Trim trailing blank line * [bsp][hpm5301evklite] Trim trailing blank line * [bsp][hpm5e00evk] Trim trailing blank line * [bsp][hpm6200evk] Trim trailing blank line * [bsp][hpm6300evk] Trim trailing blank line * [bsp][hpm6750evk] Trim trailing blank line * [bsp][hpm6750evk2] Trim trailing blank line * [bsp][hpm6750evkmini] Trim trailing blank line * [bsp][hpm6800evk] Trim trailing blank line * [bsp][hpm6e00evk] Trim trailing blank line * [bsp][nxp] switch lpc178x to gcc and remove mcx timer source * [bsp][stm32] fix the CONFIG_RT_USING_CLOCK_TIME issue. * [docs][clock_time] add clock time documentation * [docs][clock_time] Update clock time subsystem documentation - Update device driver index to use correct page reference - Clarify upper layer responsibilities in architecture overview - Update README to describe POSIX/libc, Soft RTC, and device driver usage - Refine architecture diagram with improved layout and color scheme - Remove obsolete clock_timer.md file * [kernel][utest] Trim trailing space * [clock_time] Fix hrtimer wrap handling * [clock_time] fix the static rt_inline issue * [clock_time] fix the rt_clock_hrtimer_control result issue

[lwp][rv64] riscv: fix potential signal handler infinite loop

2025-07-23T01:39:17Z

[lwp][rv64] restore tp register in arch_thread_signal_enter to fix user-mode memory access

2025-07-23T01:38:35Z

[smart] rename the Group name to 'lwProcess' and optimize the error handling for vDSO building.

2025-07-07T01:44:37Z

[smart] Add vDSO support for RISC-V architecture and refactor related components

2025-05-19T10:29:26Z

- Implemented vDSO functionality for the RISC-V architecture, including the necessary source files and linker scripts. - Introduced a new `vdso_sys.c` file for RISC-V, containing functions to handle time retrieval using the vDSO mechanism. - Created architecture-specific linker scripts (`vdso.lds.S`) for both AArch64 and RISC-V. - Updated the build system to support vDSO compilation for RISC-V, including necessary adjustments in `SConstruct` files. - Refactored existing vDSO code to improve compatibility and maintainability across architectures. - Adjusted the maximum number of PTY devices in the terminal configuration from 64 to 32 for better resource management. - Fixed minor issues in existing code, including correcting the path for the vDSO shared library and ensuring proper function definitions.

[lwp/riscv]修正用户态参数空间占用堆地址空间的问题 (#10014)

2025-02-24T01:17:22Z

* [lwp/riscv]修正用户态参数空间占用堆空间的问题

[rv]修正signal退出后用户态sp少8的问题 (#9080)

2024-06-24T13:36:32Z

[rv]信号处理进入用户态前恢复gp (#9072)

2024-06-21T01:09:41Z

* [rv/virt/stackframe.h]添加GP寄存器保存偏移量宏 * 【rv/c906/stackframe.h]定义GP寄存器存储偏移量 * [rv]信号处理切换到用户态前恢复gp