[ARCH/RISC-V] Next RISC-V (#10320)

2026-10-17T01:44:26Z

* [libcpu][risc-v] Refactor the RISC-V architecture port Introduce an opt-in unified RISC-V common layer for RV32 and RV64 while keeping existing BSPs on the legacy implementation during migration. - use ARCH_RISCV and ARCH_CPU_64BIT for architecture and XLEN selection - unify context, trap, MMU, cache, timer, SBI, SMP and ISA handling - add PLIC, CLIC, ACLINT, APLIC and IMSIC support - map physical hart IDs to contiguous logical CPU IDs - add T-Head vendor overrides while preserving legacy ports - migrate qemu-virt64-riscv with RV32 and RV64 support - update clock_time, MM, LWP, OFW, PCI and Rust integration Existing BSPs continue using legacy_common or common64 unless they select RT_USING_RISCV_NEW_COMMON. Signed-off-by: GuEe-GUI <2991707448@qq.com> * [libcpu][risc-v] skip disabled CPU nodes in early FDT walk Rbb666 noted that rt_hw_fdt_install_early() walked every /cpus child without checking status, so disabled cores still joined hart registration and MMU capability probing. Skip nodes that are not okay/ok via rt_fdt_device_is_available() before reading reg or mmu-type. Signed-off-by: seteiro * [libcpu][risc-v] Fix per-CPU page table mapping - reuse existing non-leaf page table entries when mapping per-CPU areas - reject leaf entry conflicts instead of overwriting mappings Signed-off-by: GuEe-GUI <2991707448@qq.com> --------- Signed-off-by: GuEe-GUI <2991707448@qq.com> Signed-off-by: seteiro Co-authored-by: seteiro

修改用户态 data 页权限为 RO

2026-04-29T22:19:58Z

修改锁为 rt_spinlock

2026-04-29T22:19:58Z

更新 vdso img 校验

2026-04-29T22:19:58Z

添加 vdso readtime 更新逻辑

2026-04-29T22:19:58Z

style: format code with clang-format [skip ci]

2026-04-29T22:19:58Z

解决 base_time 和 counter_last 采样不同步产生固定偏差

2026-04-29T22:19:58Z

[lwp/aarch64] Fix macro definition style in reloc.c

2026-03-12T06:39:13Z

Split the merged #define macros on line 13 into separate lines to comply with coding standards and avoid potential preprocessor issues.

rt-thread.git/components/lwp/arch, branch master

[ARCH/RISC-V] Next RISC-V (#10320)

修改用户态 data 页权限为 RO

修改锁为 rt_spinlock

更新 vdso img 校验

适配 arm 架构

添加 vdso readtime 更新逻辑

style: format code with clang-format [skip ci]

解决 base_time 和 counter_last 采样不同步产生固定偏差

更新 vdso 框架

[lwp/aarch64] Fix macro definition style in reloc.c