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<title>rt-thread.git/components/lwp/arch, branch serialX-dev</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/rt-thread.git/atom/components/lwp/arch?h=serialX-dev</id>
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<updated>2023-02-24T06:52:16Z</updated>
<entry>
<title>[rt-smart] handling kernel from accessing unmapped user stack (#6957)</title>
<updated>2023-02-24T06:52:16Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-02-24T06:52:16Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=382e9bcac746b408b5b01ea2f59338428ab203dd'/>
<id>urn:sha1:382e9bcac746b408b5b01ea2f59338428ab203dd</id>
<content type='text'>
[rt-smart] handling kernel from accessing unmapped user stack</content>
</entry>
<entry>
<title>[rt-smart] kernel virtual memory management layer (#6809)</title>
<updated>2023-01-09T02:08:55Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-01-09T02:08:55Z</published>
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<id>urn:sha1:7450ef6c4d71f992444d27f4a26c16f813ed8e55</id>
<content type='text'>
synchronize virtual memory system works.
adding kernel virtual memory management layer for page-based MMU enabled architecture
porting libcpu MMU codes
porting lwp memory related codes</content>
</entry>
<entry>
<title>[rt-smart] 弱化 RT_USING_LWP，使用 RT_USING_SMART 作为宏配置 (#6740)</title>
<updated>2022-12-16T10:38:28Z</updated>
<author>
<name>guo</name>
<email>guozhanxin@rt-thread.com</email>
</author>
<published>2022-12-16T10:38:28Z</published>
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<id>urn:sha1:68ca9f07a60ad5cbe52b37b52299327b6246e7f7</id>
<content type='text'>
* [dfs] sync cromfs

* [rt-smart]Weaken RT_USING_LWP, use RT_USING_SMART as macro configuration

* [format] fix some format issue.</content>
</entry>
<entry>
<title>[smart][risc-v/libcpu] port rv64 cpu code (#6704)</title>
<updated>2022-12-10T14:16:42Z</updated>
<author>
<name>Shell</name>
<email>maschareno@outlook.com</email>
</author>
<published>2022-12-10T14:16:42Z</published>
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<id>urn:sha1:e991be9c51c54883b56ee3d9e7f30db33c404192</id>
<content type='text'>
* [risc-v/libcpu] porting Smart &amp; RTOS
* [fix] rv64 plic
* [risc-v/rv64] remove macro in rtdef</content>
</entry>
<entry>
<title>sync branch rt-smart. (#6641)</title>
<updated>2022-12-03T04:07:44Z</updated>
<author>
<name>guo</name>
<email>guozhanxin@rt-thread.com</email>
</author>
<published>2022-12-03T04:07:44Z</published>
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<id>urn:sha1:ecf2d8215961ca7c539132b62a72df6072cc3e14</id>
<content type='text'>
* Synchronize the code of the rt mart branch to the master branch.
  * TTY device
  * Add lwP code from rt-smart
  * Add vnode in DFS, but DFS will be re-write for rt-smart
  * There are three libcpu for rt-smart:
    * arm/cortex-a, arm/aarch64
    * riscv64

Co-authored-by: Rbb666 &lt;zhangbingru@rt-thread.com&gt;
Co-authored-by: zhkag &lt;zhkag@foxmail.com&gt;</content>
</entry>
<entry>
<title>修改lwp支持中arm cortex-a的swi入口函数处理</title>
<updated>2019-04-27T05:54:51Z</updated>
<author>
<name>shaojinchun</name>
<email>shaojinchun@rt-thread.com</email>
</author>
<published>2019-04-27T05:54:51Z</published>
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<id>urn:sha1:1e7bd3d8a1082060f6cf71631849da903787d045</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Make 'qemu-vexpress-a9' and 'imx6ul' use the same libcpu code.</title>
<updated>2019-03-25T12:03:49Z</updated>
<author>
<name>qz721</name>
<email>295354721@qq.com</email>
</author>
<published>2019-03-25T12:03:49Z</published>
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<id>urn:sha1:2eb1bef773e099ac93ec74dba7ec216bdf61597c</id>
<content type='text'>
</content>
</entry>
<entry>
<title>fix lwp SConscript的头文件目录为空的问题;lwp把arm9改名成arm926</title>
<updated>2019-03-14T09:28:44Z</updated>
<author>
<name>shaojinchun</name>
<email>shaojinchun@rt-thread.com</email>
</author>
<published>2019-03-14T09:25:04Z</published>
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<id>urn:sha1:b225764b842784a7fe29cc7dfaa0ac8d4a82219f</id>
<content type='text'>
</content>
</entry>
<entry>
<title>修改许可协议</title>
<updated>2018-12-10T10:23:21Z</updated>
<author>
<name>shaojinchun</name>
<email>shaojinchun@rt-thread.com</email>
</author>
<published>2018-12-10T10:23:21Z</published>
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<id>urn:sha1:2b21d2316aaac2e04fce72a5ffb64cc7c511c9b6</id>
<content type='text'>
修改cpu目录名及相关修改
</content>
</entry>
<entry>
<title>add lwp support</title>
<updated>2018-12-10T08:44:48Z</updated>
<author>
<name>shaojinchun</name>
<email>shaojinchun@rt-thread.com</email>
</author>
<published>2018-12-10T08:31:33Z</published>
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<id>urn:sha1:a8953e92119944ffdb8c02a8d88cfa08dc3a59af</id>
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</content>
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