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<title>rt-thread.git/components/mm/SConscript, branch master</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/rt-thread.git/atom/components/mm/SConscript?h=master</id>
<link rel='self' href='http://cgit.235523.xyz/rt-thread.git/atom/components/mm/SConscript?h=master'/>
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<updated>2026-10-17T01:44:26Z</updated>
<entry>
<title>[ARCH/RISC-V] Next RISC-V (#10320)</title>
<updated>2026-10-17T01:44:26Z</updated>
<author>
<name>GUI</name>
<email>39894654+GuEe-GUI@users.noreply.github.com</email>
</author>
<published>2026-10-17T01:44:26Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=8d8dc96b67eee53af2841a8819364d52fbec39cb'/>
<id>urn:sha1:8d8dc96b67eee53af2841a8819364d52fbec39cb</id>
<content type='text'>
* [libcpu][risc-v] Refactor the RISC-V architecture port

Introduce an opt-in unified RISC-V common layer for RV32 and RV64 while keeping existing BSPs on the legacy implementation during migration.

- use ARCH_RISCV and ARCH_CPU_64BIT for architecture and XLEN selection
- unify context, trap, MMU, cache, timer, SBI, SMP and ISA handling
- add PLIC, CLIC, ACLINT, APLIC and IMSIC support
- map physical hart IDs to contiguous logical CPU IDs
- add T-Head vendor overrides while preserving legacy ports
- migrate qemu-virt64-riscv with RV32 and RV64 support
- update clock_time, MM, LWP, OFW, PCI and Rust integration

Existing BSPs continue using legacy_common or common64 unless they select RT_USING_RISCV_NEW_COMMON.

Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;

* [libcpu][risc-v] skip disabled CPU nodes in early FDT walk

Rbb666 noted that rt_hw_fdt_install_early() walked every /cpus child
without checking status, so disabled cores still joined hart registration
and MMU capability probing. Skip nodes that are not okay/ok via
rt_fdt_device_is_available() before reading reg or mmu-type.

Signed-off-by: seteiro &lt;chenmoushun@163.com&gt;

* [libcpu][risc-v] Fix per-CPU page table mapping

- reuse existing non-leaf page table entries when mapping per-CPU areas
- reject leaf entry conflicts instead of overwriting mappings

Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;

---------

Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;
Signed-off-by: seteiro &lt;chenmoushun@163.com&gt;
Co-authored-by: seteiro &lt;chenmoushun@163.com&gt;</content>
</entry>
<entry>
<title>fix(mm): exclude no-MMU ioremap from MMU builds</title>
<updated>2026-08-12T04:54:50Z</updated>
<author>
<name>Rbb666</name>
<email>zhangbingru@rt-thread.com</email>
</author>
<published>2026-07-31T08:23:18Z</published>
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<id>urn:sha1:f05fb1c0760f4791e22c62633650d9d52dc764af</id>
<content type='text'>
</content>
</entry>
<entry>
<title>feat(dm): support OFW on Cortex-M targets</title>
<updated>2026-08-12T04:54:50Z</updated>
<author>
<name>Rbb666</name>
<email>zhangbingru@rt-thread.com</email>
</author>
<published>2026-07-31T07:07:36Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=6b4f34204ed2da80b7c37b912612c65cebc30ce3'/>
<id>urn:sha1:6b4f34204ed2da80b7c37b912612c65cebc30ce3</id>
<content type='text'>
Add the ARM NVIC PIC driver, no-MMU I/O mapping, built-in FDT support, and Cortex-M CPU hooks required by the native RT-Thread device model.
</content>
</entry>
<entry>
<title>utest: move mm testcases to components/mm</title>
<updated>2026-06-12T06:22:53Z</updated>
<author>
<name>CYFS</name>
<email>2805686936@qq.com</email>
</author>
<published>2026-06-11T06:40:29Z</published>
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<id>urn:sha1:f559dceeb55d357684529fbfc3a1241062ee5a17</id>
<content type='text'>
Signed-off-by: CYFS &lt;2805686936@qq.com&gt;
</content>
</entry>
<entry>
<title>Reorganize Group names in build system for clarity and IDE integration #10923</title>
<updated>2025-11-16T03:40:53Z</updated>
<author>
<name>Copilot</name>
<email>198982749+Copilot@users.noreply.github.com</email>
</author>
<published>2025-11-16T03:40:53Z</published>
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<id>urn:sha1:30e1e5e9dcdaff17258edf70b9f9783e08356288</id>
<content type='text'>
</content>
</entry>
<entry>
<title>component:mm: improve sconscript (#9028)</title>
<updated>2024-06-05T02:04:32Z</updated>
<author>
<name>Chen Wang</name>
<email>unicorn_wang@outlook.com</email>
</author>
<published>2024-06-05T02:04:32Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=f0af6ef809f4c258c89943d5a7980ae8308839ab'/>
<id>urn:sha1:f0af6ef809f4c258c89943d5a7980ae8308839ab</id>
<content type='text'>
There is no next-level directory under the components/mm/
directory. Do not need to enter the next-level directory
to process the SConscript file.

Signed-off-by: Chen Wang &lt;unicorn_wang@outlook.com&gt;</content>
</entry>
<entry>
<title>Sync dfs lwp (#8123)</title>
<updated>2023-10-17T05:07:59Z</updated>
<author>
<name>geniusgogo</name>
<email>2041245+geniusgogo@users.noreply.github.com</email>
</author>
<published>2023-10-17T05:07:59Z</published>
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<id>urn:sha1:ecd29fda6005ef19c625f194f9311259ba907a78</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[components][mm]添加预留内存支持 (#8025)</title>
<updated>2023-10-14T06:10:57Z</updated>
<author>
<name>zms123456</name>
<email>85141075+zmshahaha@users.noreply.github.com</email>
</author>
<published>2023-10-14T06:10:57Z</published>
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<id>urn:sha1:a39da9cb596b9dc0b0d0265fa67d5db8a2f66f09</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[rt-smart/mm] enable mm on armv7, armv8, rv64 only (#6834)</title>
<updated>2023-01-11T08:24:51Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-01-11T08:24:51Z</published>
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<id>urn:sha1:12189d533a538e4b7f936314ab28c2625c0cb860</id>
<content type='text'>
* [mm] enable mm on armv7, armv8, rv64 only

* [mm] config on ARCH_MM_MMU</content>
</entry>
<entry>
<title>format Kconfig and sconscript</title>
<updated>2023-01-09T03:52:13Z</updated>
<author>
<name>Meco Man</name>
<email>920369182@qq.com</email>
</author>
<published>2023-01-09T02:14:23Z</published>
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<id>urn:sha1:9bc68d26a446158aad13f910fa5a2b8b09febec1</id>
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</content>
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