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<title>rt-thread.git/components/mm, branch v5.0.1</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/rt-thread.git/atom/components/mm?h=v5.0.1</id>
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<updated>2023-05-23T14:43:38Z</updated>
<entry>
<title>add lstat&amp;sysinfo....syscall. (#7555)</title>
<updated>2023-05-23T14:43:38Z</updated>
<author>
<name>geniusgogo</name>
<email>2041245+geniusgogo@users.noreply.github.com</email>
</author>
<published>2023-05-23T14:43:38Z</published>
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<id>urn:sha1:0315c0dee76ce67e3659744d4d280659e0a13906</id>
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</content>
</entry>
<entry>
<title>[libcpu/aarch64] fix cache invalidate operation (#7363)</title>
<updated>2023-04-26T09:17:42Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-04-26T09:17:42Z</published>
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<id>urn:sha1:6e7c5d9bc9f9b5491bd9edd702d20867a92b5ec5</id>
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</entry>
<entry>
<title>[components/mm] support for scalable memory management (#7277)</title>
<updated>2023-04-22T15:59:11Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-04-22T15:59:11Z</published>
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<id>urn:sha1:470454d201ebb89aa72525f8c3fb562e372f4f56</id>
<content type='text'>
* [mm/page] multi-list page manager
[mm/page] page debugger
[libcpu/aarch64] hugepage support

* [quality] remove void-arith

* [format] remove kasan codes</content>
</entry>
<entry>
<title>fix warning (#7340)</title>
<updated>2023-04-22T01:25:52Z</updated>
<author>
<name>xiaoniaoyou6hua</name>
<email>74241971+xiaoniaoyou6hua@users.noreply.github.com</email>
</author>
<published>2023-04-22T01:25:52Z</published>
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<id>urn:sha1:4f1c3a1472e3ffc550a3c51d1346b2b202e7c5ad</id>
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</content>
</entry>
<entry>
<title>[fix] compilation error from rpi (#7143)</title>
<updated>2023-03-31T12:58:01Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-03-31T12:58:01Z</published>
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<id>urn:sha1:897ba365baa1cb2105b46964082d378e7b14b47b</id>
<content type='text'>
* [fix] compile error from rpi</content>
</entry>
<entry>
<title>[rt-smart] testcase &amp; improvements for memory management (#7099)</title>
<updated>2023-03-30T00:25:15Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-03-30T00:25:15Z</published>
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<id>urn:sha1:eec78d9f5d3f0a944500a1cac5802dfee2befc7b</id>
<content type='text'>
* [utest/mm] add testcase for create/init
format codes of create/init in components/mm

* [libcpu/aarch64] fix user stack check routine

* [kservice] export API for utest

* [utest/mm] testcase for aspace_map
format &amp; modify the files under components/mm related with aspace_map

* [lwp/user_mm] add user_map_varea for mmap feature

* [mm] rename rt_mm_fault_try_fix to rt_aspace_fault_try_fix

* [utest/mm] testcase for synchronization

* [mm] modify unmap api to improve throughput

* [utest/mm] testcases for cache and varea map

* [format] remove extra space

* [utest/mm] fix testcase problem in header

* [lwp] extend map_user_varea with a flag

* [utest/mm] testcase for lwp_map_user_varea

* [libcpu/arm/cortex-a] fix kernel space layout

* [utest/mm] adjust for armv7 arch</content>
</entry>
<entry>
<title>[rt-smart] fix competition on aspace (#7064)</title>
<updated>2023-03-19T06:41:50Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-03-19T06:41:50Z</published>
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<id>urn:sha1:dd2f1a795af0674f0d2f2c23df721fb8decbafb8</id>
<content type='text'>
* [mm] mmu operations should be wrapped by _aspace_bst_insert &amp; _aspace_bst_remove to avoid competition on page table

* [lwp] may not return null on failed</content>
</entry>
<entry>
<title>[rt-smart] move sys_cacheflush to lwp_syscall.c (#7048)</title>
<updated>2023-03-17T07:11:38Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-03-17T07:11:38Z</published>
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<id>urn:sha1:18a14cc9351e9c44df539ad21ce825679bc023ca</id>
<content type='text'>
* [syscall] move sys_cacheflush to lwp_syscall.c

* [syscall] improve assertion

* [format] rename to rt_ctassert

* [debug] modified ct assertion on mm_page.c</content>
</entry>
<entry>
<title>[components][mm] add ioremap for normal memory api (#7050)</title>
<updated>2023-03-16T02:27:16Z</updated>
<author>
<name>张世争</name>
<email>zhangshizheng@rt-thread.com</email>
</author>
<published>2023-03-16T02:27:16Z</published>
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<id>urn:sha1:334c609c6c38a3bd30275bfb4bb563b6c160860a</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[libcpu/risc-v] support noncached normal memory (#7051)</title>
<updated>2023-03-16T02:26:55Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-03-16T02:26:55Z</published>
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<id>urn:sha1:2394e75265891c83e3b9a00634a30c9ef1c7b13a</id>
<content type='text'>
* [libcpu/risc-v] support noncached normal memory

* [mm] check before dereference in _fetch_page

* [mm] add comments on ioremap

* [ioremap] report more info on failed</content>
</entry>
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