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<title>rt-thread.git/include/rthw.h, branch v5.0.x</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/rt-thread.git/atom/include/rthw.h?h=v5.0.x</id>
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<updated>2023-03-31T02:56:37Z</updated>
<entry>
<title>✨ feat(components): add uname support</title>
<updated>2023-03-31T02:56:37Z</updated>
<author>
<name>xqyjlj</name>
<email>xqyjlj@126.com</email>
</author>
<published>2023-03-27T09:09:37Z</published>
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<id>urn:sha1:157dc0959c30ef0296cfa582d9ae8e610a0f0709</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[fixup] add cache maintenance ops;</title>
<updated>2023-02-21T00:48:49Z</updated>
<author>
<name>wangxiaoyao</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-02-20T05:48:00Z</published>
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<id>urn:sha1:484a0d602e8b571a9d8186d38c8b136abc4ccfc9</id>
<content type='text'>
fix bugs on cache maintenance when starting user app
</content>
</entry>
<entry>
<title>[rt-smart] kernel virtual memory management layer (#6809)</title>
<updated>2023-01-09T02:08:55Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-01-09T02:08:55Z</published>
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<id>urn:sha1:7450ef6c4d71f992444d27f4a26c16f813ed8e55</id>
<content type='text'>
synchronize virtual memory system works.
adding kernel virtual memory management layer for page-based MMU enabled architecture
porting libcpu MMU codes
porting lwp memory related codes</content>
</entry>
<entry>
<title>sync branch rt-smart. (#6641)</title>
<updated>2022-12-03T04:07:44Z</updated>
<author>
<name>guo</name>
<email>guozhanxin@rt-thread.com</email>
</author>
<published>2022-12-03T04:07:44Z</published>
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<id>urn:sha1:ecf2d8215961ca7c539132b62a72df6072cc3e14</id>
<content type='text'>
* Synchronize the code of the rt mart branch to the master branch.
  * TTY device
  * Add lwP code from rt-smart
  * Add vnode in DFS, but DFS will be re-write for rt-smart
  * There are three libcpu for rt-smart:
    * arm/cortex-a, arm/aarch64
    * riscv64

Co-authored-by: Rbb666 &lt;zhangbingru@rt-thread.com&gt;
Co-authored-by: zhkag &lt;zhkag@foxmail.com&gt;</content>
</entry>
<entry>
<title>[update] Fix some spelling mistakes. (#5738)</title>
<updated>2022-03-29T13:29:08Z</updated>
<author>
<name>guo</name>
<email>guozhanxin@rt-thread.com</email>
</author>
<published>2022-03-29T13:29:08Z</published>
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<id>urn:sha1:b2e2ab28e51a1522098e2bee8bf4157a838c7cdd</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[libcpu/aarch64] add gicv3 support and bsp/rockchip/rk3568 (#5722)</title>
<updated>2022-03-29T03:08:25Z</updated>
<author>
<name>GUI</name>
<email>39894654+GuEe-GUI@users.noreply.github.com</email>
</author>
<published>2022-03-29T03:08:25Z</published>
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<id>urn:sha1:f587a55bc2006f4316383425d518b734e42bb4a2</id>
<content type='text'>
* [libcpu/aarch64] add smp support

* [libcpu/aarch64] rt_hw_trap_irq get irq instead of iar when using gicv2

* [libcpu/aarch64] disable irq/fiq when switch thread

* [libcpu/aarch64] add gtimer frq set and stack align

* [libcpu/aarch64] add gicv3 support and bsp/rockchip/rk3568</content>
</entry>
<entry>
<title>[include] auto formatted</title>
<updated>2021-03-08T09:22:21Z</updated>
<author>
<name>Meco Man</name>
<email>920369182@qq.com</email>
</author>
<published>2021-03-08T09:22:21Z</published>
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<id>urn:sha1:2fd265406edc642dc083ecc76b286611b4585c64</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[kernel] code and comments cleanup</title>
<updated>2019-12-16T05:59:46Z</updated>
<author>
<name>Bernard Xiong</name>
<email>bernard.xiong@gmail.com</email>
</author>
<published>2019-12-16T05:59:46Z</published>
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<id>urn:sha1:992d3af3aee1e8567080e33e27011170f60dfab9</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[Kernel] cleanup code of spinlock in SMP Kernel</title>
<updated>2019-09-28T03:56:03Z</updated>
<author>
<name>Bernard Xiong</name>
<email>bernard.xiong@gmail.com</email>
</author>
<published>2019-09-28T03:56:03Z</published>
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<id>urn:sha1:5cd65092967a1dbaa35bb7fdd80cf3a0e2f9cc9f</id>
<content type='text'>
</content>
</entry>
<entry>
<title>开放spinlock相关函数</title>
<updated>2019-09-27T06:38:33Z</updated>
<author>
<name>shaojinchun</name>
<email>shaojinchun@rt-thread.com</email>
</author>
<published>2019-09-26T10:13:07Z</published>
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<id>urn:sha1:cb07e5fb24afebdf233847da551d3ede80727345</id>
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</content>
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