rt-thread.git/libcpu/Kconfig, branch v5.2.0-beta

feat: Kconfig: moving the arm64 specified configs to sub-menu

2024-11-24T18:44:34Z

Just for better readability. Signed-off-by: Shell

feat: arm64 ASID support

2024-11-24T18:44:34Z

Support for ARM64 ASID to enhance virtual memory management efficiency by reducing the need for TLB flushes during address space switches. These changes improve performance especially for multi-process systems. Changes: - Added `ARCH_USING_ASID` configuration in `libcpu/aarch64/Kconfig`. - Defined ASID-related constants in `mmu.h`. - Updated `TLBI_ARG` macro to include ASID manipulation. - Implemented ASID allocation mechanism with spinlock synchronization. - Enhanced TLB invalidation to support ASID-specific operations. - Modified `rt_hw_aspace_switch` to use ASIDs when switching address spaces. - Adjusted debug logging and function documentation to reflect ASID usage. - Refactored AArch64 MMU and TLB handling for ASID integration. Signed-off-by: Shell

feat: Added rt_interrupt_context* family for nested interrupt handling

2024-11-03T02:08:45Z

These changes introduce the rt_interrupt_context family, providing a mechanism for managing nested interrupts. The context management ensures proper storage and retrieval of interrupt states, improving reliability in nested interrupt scenarios by enabling context tracking across different interrupt levels. This enhancement is essential for platforms where nested interrupt handling is crucial, such as in real- time or multi-threaded applications. Changes: - Defined rt_interrupt_context structure with context and node fields in `rtdef.h` to support nested interrupts. - Added rt_slist_pop function in `rtservice.h` for simplified node removal in singly linked lists. - Declared rt_interrupt_context_push, rt_interrupt_context_pop, and rt_interrupt_context_get functions in `rtthread.h` to manage the interrupt/exception stack. - Modified AArch64 CPU support in `cpuport.h` to include rt_hw_show_register for debugging registers. - Refactored `_rt_hw_trap_irq` in `trap.c` for context-aware IRQ handling, with stack push/pop logic to handle nested contexts. - Implemented interrupt context push, pop, and retrieval logic in `irq.c` to manage context at the CPU level. Signed-off-by: Shell

[libcpu][cortex-m7] use hw atomic

2024-11-01T22:45:00Z

[libcpu]添加对riscv vector的支持 (#9531)

2024-10-16T06:10:09Z

[libcpu]添加对riscv vector的支持

feat: libcpu/risc-v: unify context on c906, virt64

2024-09-11T22:06:51Z

Changes: - added config for NEW_CTX_SWITCH - used new context on c906 sched switch routine - update _rt_hw_stack_init to fit into NEW_CTX_SWITCH - separated vector ctx from the generic Signed-off-by: Shell

[libcpu/rv64] feat: unify tick.c

2024-07-15T04:06:39Z

The changes unify the tick.c implementations for all risc-v64 architectures, leveraging the CPUTIME feature. This refactoring was necessary to streamline the codebase, and ensure consistent timer handling across different platforms. Changes: - Updated `Kconfig` in `bsp/cvitek/cv18xx_risc-v` to fix formatting issues. - Updated .config for BSPs to update `CPUTIME_TIMER_FREQ` - Updated header of for API `riscv_cputime_init` - Initialized riscv timer on `rt_hw_tick_init` - Refactored `tick.c` and `tick.h` in `libcpu/risc-v/t-head/c906` and `libcpu/risc-v/virt64`: - Replaced direct use of `rdtime` with `clock_cpu_gettime`. - Removed redundant timer frequency definitions. - Added static assertions to check the value of `CPUTIME_TIMER_FREQ`. - Initialized `tick_cycles` based on `CPUTIME_TIMER_FREQ`. - Integrated `ktime` support for tick initialization. Signed-off-by: Shell Reviewed-on: https://github.com/RT-Thread/rt-thread/pull/9164 Reviewed-by: Chen Wang

feat: support ARCH_REMAP_KERNEL on libcpu/c906 (#9123)

2024-07-11T03:00:04Z

feat: [libcpu/c906] support ARCH_REMAP_KERNEL This change was necessary to enable the remapping of the kernel image to a high virtual address region on the c906 platform. Changes: - Introduced new configuration options `ARCH_REMAP_KERNEL`, and `ARCH_USING_ASID` under the `ARCH_RISCV64` section. - Updated MMU initialization and switching functions to incorporate remapping handling. - Modified page table setup for proper memory attribute settings. - Added support for early memory setup, kernel remapping - Added conditional compilation for ASID support in the `rt_aspace` struct, since this is not enable currently for most architecture. Signed-off-by: Shell

[libcpu][aarch64]memory setup using memblock (#9092)

2024-06-26T06:36:49Z

* memory setup using memblock * map pages later

[libcpu] rv64: support for ARCH_REMAP_KERNEL (#9067)

2024-06-18T03:15:59Z

* [libcpu] support for ARCH_REMAP_KERNEL These changes introduce support for the ARCH_REMAP_KERNEL configuration, which isolates kernel space in high virtual address regions. This feature is necessary to enhance memory protection and management by segregating user and kernel spaces more effectively. Changes: - Updated conditional macros to check for ARCH_REMAP_KERNEL instead of ARCH_KERNEL_IN_HIGH_VA in board initialization files to reflect the new configuration option. - Modified qemu-virt64-riscv Kconfig and SConstruct files to include and utilize ARCH_REMAP_KERNEL. - Created a new linker script `link_smart.lds` for smart linking in qemu-virt64-riscv. - Updated rtconfig.py to use a more flexible execution path setup. - Enhanced user address space definitions in `lwp_arch.h` to support the new virtual address mappings. - Adjusted kernel memory initialization and mapping logic in `c906/mmu.c` and `virt64/mmu.c` to account for high virtual address regions. - Added Kconfig option to enable ARCH_REMAP_KERNEL for RISCV64 architectures. - Enhanced memory setup functions to support new mapping scheme, including updates to early page table setup and address relocation logic. These modifications ensure that the system can utilize high memory addresses for the kernel, improving memory isolation and system stability. Signed-off-by: Shell * fixup: CI run failed * bsp: default config without using smart * fixup: static checks * restore rt_hw_mmu_kernel_map_init for D1 --------- Signed-off-by: Shell