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<title>rt-thread.git/libcpu/aarch64/common/context_gcc.S, branch v5.0.2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/rt-thread.git/atom/libcpu/aarch64/common/context_gcc.S?h=v5.0.2</id>
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<updated>2023-09-16T03:52:42Z</updated>
<entry>
<title>[libcpu/aarch64] fix compile error (#8045)</title>
<updated>2023-09-16T03:52:42Z</updated>
<author>
<name>Shell</name>
<email>smokewood@qq.com</email>
</author>
<published>2023-09-16T03:52:42Z</published>
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<id>urn:sha1:b0deb61bc4768bc82f9e7e1896ed0669eeb9de7e</id>
<content type='text'>
Signed-off-by: Shell &lt;smokewood@qq.com&gt;</content>
</entry>
<entry>
<title>update components &amp; lwp. (#7888)</title>
<updated>2023-08-07T16:22:14Z</updated>
<author>
<name>geniusgogo</name>
<email>2041245+geniusgogo@users.noreply.github.com</email>
</author>
<published>2023-08-07T16:22:14Z</published>
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<id>urn:sha1:4d20416b2f62cbb6c98e88223d6a0d1638b7f1c0</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[libcpu/arm] fix race condition with ldrex,strex (#7842)</title>
<updated>2023-07-25T06:07:44Z</updated>
<author>
<name>Shell</name>
<email>smokewood@qq.com</email>
</author>
<published>2023-07-25T06:07:44Z</published>
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<id>urn:sha1:acfa74f078b23d670ad04c3a2aa9cec5fbcf5afe</id>
<content type='text'>
Signed-off-by: Shell &lt;smokewood@qq.com&gt;</content>
</entry>
<entry>
<title>AMP-step3: 添加conifg ARCH_ARM_CORTEX_A55， rt_hw_cpu_id_set 适配A55架构, 添加aarch64 rt_… (#7628)</title>
<updated>2023-06-10T23:06:16Z</updated>
<author>
<name>wangqinglin</name>
<email>53550140+HelloByeAll@users.noreply.github.com</email>
</author>
<published>2023-06-10T23:06:16Z</published>
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<id>urn:sha1:194a2efdf4b65531c3149f5a3bb0154b35514abd</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[libcpu][component][debug] add debug info for gdb (#7033)</title>
<updated>2023-05-14T15:48:16Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-05-14T15:48:16Z</published>
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<id>urn:sha1:b7554a70d21582cab97028477941fb692ef248b8</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[bsp][phytium]适配rt-thread5.0.0 版本 (#7441)</title>
<updated>2023-05-11T02:25:21Z</updated>
<author>
<name>huanghe</name>
<email>31907499+ssd4561@users.noreply.github.com</email>
</author>
<published>2023-05-11T02:25:21Z</published>
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<id>urn:sha1:50a4e8c6625694eedfc2f4db20951daed754c4a3</id>
<content type='text'>
Co-authored-by: 朱耿宇 &lt;zhugengyu@phytium.com.cn&gt;</content>
</entry>
<entry>
<title>[rt-smart] kernel virtual memory management layer (#6809)</title>
<updated>2023-01-09T02:08:55Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-01-09T02:08:55Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=7450ef6c4d71f992444d27f4a26c16f813ed8e55'/>
<id>urn:sha1:7450ef6c4d71f992444d27f4a26c16f813ed8e55</id>
<content type='text'>
synchronize virtual memory system works.
adding kernel virtual memory management layer for page-based MMU enabled architecture
porting libcpu MMU codes
porting lwp memory related codes</content>
</entry>
<entry>
<title>[smart/aarch64] code sync (#6750)</title>
<updated>2022-12-20T09:49:37Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2022-12-20T09:49:37Z</published>
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<id>urn:sha1:e8504c7cf1d03c07608e2197eaef728a6aecde7a</id>
<content type='text'>
* [smart/aarch64] sync aarch64</content>
</entry>
<entry>
<title>[libcpu/aarch64] add gtimer frq set and stack align (#5642)</title>
<updated>2022-03-07T14:41:56Z</updated>
<author>
<name>GUI</name>
<email>39894654+GuEe-GUI@users.noreply.github.com</email>
</author>
<published>2022-03-07T14:41:56Z</published>
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<id>urn:sha1:0a8dd10b0bb73a8c52b7c9132bdb9ce8202a18bb</id>
<content type='text'>
* [libcpu/aarch64] add smp support

* [libcpu/aarch64] rt_hw_trap_irq get irq instead of iar when using gicv2

* [libcpu/aarch64] disable irq/fiq when switch thread

* [libcpu/aarch64] add gtimer frq set and stack align</content>
</entry>
<entry>
<title>[libcpu/aarch64] disable irq/fiq when switch thread (#5605)</title>
<updated>2022-02-21T15:24:51Z</updated>
<author>
<name>GUI</name>
<email>39894654+GuEe-GUI@users.noreply.github.com</email>
</author>
<published>2022-02-21T15:24:51Z</published>
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<id>urn:sha1:9b6e75f90b1e56c075eb2bb2566dfd6843a2b5e2</id>
<content type='text'>
* [libcpu/aarch64] add smp support

* [libcpu/aarch64] rt_hw_trap_irq get irq instead of iar when using gicv2

* [libcpu/aarch64] disable irq/fiq when switch thread</content>
</entry>
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