rt-thread.git/libcpu/aarch64/common/cpu_gcc.S, branch v5.3.0

aarch64: document the CNTFRQ_EL0

2025-10-23T14:08:05Z

Signed-off-by: Yonggang Luo

[format] cleanup libcpu/aarch64 (#8950)

2024-06-27T16:23:09Z

* [dfs] fixup compiler warning Signed-off-by: Shell * [format] libcpu/arm64: separate context switching codes Signed-off-by: Shell * [format] libcpu/arm64: separate vector Signed-off-by: Shell * [format] libcpu/arm64: separate context_gcc.S Signed-off-by: Shell * [format] libcpu/arm64: moving headers to include directory Signed-off-by: Shell * style: replace tab with space --------- Signed-off-by: Shell

[libcpu/arm64] add C11 atomic ticket spinlock (#8882)

2024-05-16T07:45:12Z

* [libcpu/arm64] add C11 atomic ticket spinlock Replace the former implementation of flag-based spinlock which is unfair Besides, C11 atomic implementation is more readable (it's C anyway), and maintainable. Cause toolchain can use their builtin optimization and tune for different micro-architectures. For example armv8.5 introduces a better instruction. The compiler can help with that when it knows your target platform in support of it. Signed-off-by: Shell * fixup: RT_CPUS_NR --------- Signed-off-by: Shell

[smart/aarch64] code sync (#6750)

2022-12-20T09:49:37Z

* [smart/aarch64] sync aarch64

[asm] 解决tab和空格混用的问题

2022-01-20T12:57:35Z

add raspi4 bsp

2020-04-16T08:44:14Z