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<title>rt-thread.git/libcpu/aarch64/common/interrupt.c, branch v5.0.2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/rt-thread.git/atom/libcpu/aarch64/common/interrupt.c?h=v5.0.2</id>
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<updated>2023-06-26T13:30:27Z</updated>
<entry>
<title>修复gicv2默认邦核失败 (#7723)</title>
<updated>2023-06-26T13:30:27Z</updated>
<author>
<name>wangqinglin</name>
<email>53550140+HelloByeAll@users.noreply.github.com</email>
</author>
<published>2023-06-26T13:30:27Z</published>
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<id>urn:sha1:d6f6ae56fdd562a110516adfc9d68bbd33b8f3bf</id>
<content type='text'>
</content>
</entry>
<entry>
<title>更新gicv3中断亲和性设置，重构api: arm_gic_send_affinity_sgi, 增加AMP宏判断,  rt_ioremap和宏RT_USING_SMART解耦</title>
<updated>2023-06-19T03:35:46Z</updated>
<author>
<name>wangqinglin</name>
<email>53550140+HelloByeAll@users.noreply.github.com</email>
</author>
<published>2023-06-05T09:53:22Z</published>
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<id>urn:sha1:8335c5add2b311d15e6529d1193a6601e0515239</id>
<content type='text'>
修改:中断安装默认绑定至当前核心， 修改rt_hw_interrupt_set_target_cpus函数,
</content>
</entry>
<entry>
<title>[bsp][phytium]适配rt-thread5.0.0 版本 (#7441)</title>
<updated>2023-05-11T02:25:21Z</updated>
<author>
<name>huanghe</name>
<email>31907499+ssd4561@users.noreply.github.com</email>
</author>
<published>2023-05-11T02:25:21Z</published>
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<id>urn:sha1:50a4e8c6625694eedfc2f4db20951daed754c4a3</id>
<content type='text'>
Co-authored-by: 朱耿宇 &lt;zhugengyu@phytium.com.cn&gt;</content>
</entry>
<entry>
<title>优化设置中断模式api (#7359)</title>
<updated>2023-04-24T06:16:21Z</updated>
<author>
<name>wangqinglin</name>
<email>53550140+HelloByeAll@users.noreply.github.com</email>
</author>
<published>2023-04-24T06:16:21Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=ac07f40670addad74b5cde0c46d6d9cfe6722fe0'/>
<id>urn:sha1:ac07f40670addad74b5cde0c46d6d9cfe6722fe0</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[rt-smart] kernel virtual memory management layer (#6809)</title>
<updated>2023-01-09T02:08:55Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-01-09T02:08:55Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=7450ef6c4d71f992444d27f4a26c16f813ed8e55'/>
<id>urn:sha1:7450ef6c4d71f992444d27f4a26c16f813ed8e55</id>
<content type='text'>
synchronize virtual memory system works.
adding kernel virtual memory management layer for page-based MMU enabled architecture
porting libcpu MMU codes
porting lwp memory related codes</content>
</entry>
<entry>
<title>[smart/aarch64] code sync (#6750)</title>
<updated>2022-12-20T09:49:37Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2022-12-20T09:49:37Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=e8504c7cf1d03c07608e2197eaef728a6aecde7a'/>
<id>urn:sha1:e8504c7cf1d03c07608e2197eaef728a6aecde7a</id>
<content type='text'>
* [smart/aarch64] sync aarch64</content>
</entry>
<entry>
<title>[libcpu/aarch64] add gicv3 support and bsp/rockchip/rk3568 (#5722)</title>
<updated>2022-03-29T03:08:25Z</updated>
<author>
<name>GUI</name>
<email>39894654+GuEe-GUI@users.noreply.github.com</email>
</author>
<published>2022-03-29T03:08:25Z</published>
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<id>urn:sha1:f587a55bc2006f4316383425d518b734e42bb4a2</id>
<content type='text'>
* [libcpu/aarch64] add smp support

* [libcpu/aarch64] rt_hw_trap_irq get irq instead of iar when using gicv2

* [libcpu/aarch64] disable irq/fiq when switch thread

* [libcpu/aarch64] add gtimer frq set and stack align

* [libcpu/aarch64] add gicv3 support and bsp/rockchip/rk3568</content>
</entry>
<entry>
<title>[libcpu/aarch64] rt_hw_trap_irq get irq instead of iar when using gicv2 (#5601)</title>
<updated>2022-02-16T17:00:29Z</updated>
<author>
<name>GUI</name>
<email>39894654+GuEe-GUI@users.noreply.github.com</email>
</author>
<published>2022-02-16T17:00:29Z</published>
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<id>urn:sha1:85dc9bd4a6e798c74f16a87bc91191907dfdbaf7</id>
<content type='text'>
* [libcpu/aarch64] add smp support
* [libcpu/aarch64] rt_hw_trap_irq get irq instead of iar when using gicv2</content>
</entry>
<entry>
<title>[libcpu/aarch64] add smp support</title>
<updated>2022-01-08T10:24:02Z</updated>
<author>
<name>GuEe-GUI</name>
<email>2991707448@qq.com</email>
</author>
<published>2022-01-07T05:49:06Z</published>
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<id>urn:sha1:353f717037b57f663ddce9447fd05700f3087a66</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Merge AArch64 libcpu and add some drivers for their bsps</title>
<updated>2021-09-26T07:01:59Z</updated>
<author>
<name>GuEe-GUI</name>
<email>2991707448@qq.com</email>
</author>
<published>2021-09-22T09:57:45Z</published>
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<id>urn:sha1:740cd9dfb013a26cb5a9106a717deedd4478eff5</id>
<content type='text'>
</content>
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