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<title>rt-thread.git/libcpu/aarch64/common/stack.c, branch master</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/rt-thread.git/atom/libcpu/aarch64/common/stack.c?h=master</id>
<link rel='self' href='http://cgit.235523.xyz/rt-thread.git/atom/libcpu/aarch64/common/stack.c?h=master'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/'/>
<updated>2024-07-18T09:41:48Z</updated>
<entry>
<title>[libcpu/arm64] feat: Trimming General Context</title>
<updated>2024-07-18T09:41:48Z</updated>
<author>
<name>Shell</name>
<email>smokewood@qq.com</email>
</author>
<published>2024-04-18T09:12:10Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=7138f340b2c1cf002779a45d73c4d30295d44c58'/>
<id>urn:sha1:7138f340b2c1cf002779a45d73c4d30295d44c58</id>
<content type='text'>
This patch focuses on the ARM64 general context handling code.
The modifications are aimed at enhancing performance by simplifying
context save/restore operations.

Changes include:
- Adjusted stack alignment in `arch_set_thread_context` function.
- Updated `lwp_gcc.S` to reset frame pointer and link register.
- Refined `rt_hw_backtrace_frame_unwind` to handle user space address checks.
- Added `GET_THREAD_SELF` macro in `asm-generic.h`.
- Simplified context saving/restoring in `context_gcc.h` and related files.
- Optimized `rt_hw_context_switch_interrupt` and related assembly routines.

Signed-off-by: Shell &lt;smokewood@qq.com&gt;
</content>
</entry>
<entry>
<title>[bsp/rpi4] fixup startup failure (#8754)</title>
<updated>2024-04-10T16:02:49Z</updated>
<author>
<name>Shell</name>
<email>smokewood@qq.com</email>
</author>
<published>2024-04-10T16:02:49Z</published>
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<id>urn:sha1:b14e0c08e1e540a4634fb493a44be95ba679c0d5</id>
<content type='text'>
[bsp/rpi4] fixup startup issues

Signed-off-by: Shell &lt;smokewood@qq.com&gt;</content>
</entry>
<entry>
<title>AArch64: fixup fpu storage's size in stack and append Q16 ~ Q31 (#7815)</title>
<updated>2023-07-15T07:21:23Z</updated>
<author>
<name>GUI</name>
<email>39894654+GuEe-GUI@users.noreply.github.com</email>
</author>
<published>2023-07-15T07:21:23Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=b424169e1742c1b19d039f9871dd3c672ea7b729'/>
<id>urn:sha1:b424169e1742c1b19d039f9871dd3c672ea7b729</id>
<content type='text'>
Signed-off-by: GuEe-GUI &lt;GuEe-GUI@github.com&gt;</content>
</entry>
<entry>
<title>[libcpu][component][debug] add debug info for gdb (#7033)</title>
<updated>2023-05-14T15:48:16Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-05-14T15:48:16Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=b7554a70d21582cab97028477941fb692ef248b8'/>
<id>urn:sha1:b7554a70d21582cab97028477941fb692ef248b8</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[smart/aarch64] code sync (#6750)</title>
<updated>2022-12-20T09:49:37Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2022-12-20T09:49:37Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=e8504c7cf1d03c07608e2197eaef728a6aecde7a'/>
<id>urn:sha1:e8504c7cf1d03c07608e2197eaef728a6aecde7a</id>
<content type='text'>
* [smart/aarch64] sync aarch64</content>
</entry>
<entry>
<title>[libcpu/aarch64] add gtimer frq set and stack align (#5642)</title>
<updated>2022-03-07T14:41:56Z</updated>
<author>
<name>GUI</name>
<email>39894654+GuEe-GUI@users.noreply.github.com</email>
</author>
<published>2022-03-07T14:41:56Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=0a8dd10b0bb73a8c52b7c9132bdb9ce8202a18bb'/>
<id>urn:sha1:0a8dd10b0bb73a8c52b7c9132bdb9ce8202a18bb</id>
<content type='text'>
* [libcpu/aarch64] add smp support

* [libcpu/aarch64] rt_hw_trap_irq get irq instead of iar when using gicv2

* [libcpu/aarch64] disable irq/fiq when switch thread

* [libcpu/aarch64] add gtimer frq set and stack align</content>
</entry>
<entry>
<title>[libcpu/aarch64] add smp support</title>
<updated>2022-01-08T10:24:02Z</updated>
<author>
<name>GuEe-GUI</name>
<email>2991707448@qq.com</email>
</author>
<published>2022-01-07T05:49:06Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=353f717037b57f663ddce9447fd05700f3087a66'/>
<id>urn:sha1:353f717037b57f663ddce9447fd05700f3087a66</id>
<content type='text'>
</content>
</entry>
<entry>
<title>fixup .bss size define in link.lds and set spsel=1 in aarch64</title>
<updated>2021-11-30T03:14:17Z</updated>
<author>
<name>GuEe-GUI</name>
<email>2991707448@qq.com</email>
</author>
<published>2021-11-30T02:32:23Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=efbdbc2636abf25d0836d58a666b91d61b99bf80'/>
<id>urn:sha1:efbdbc2636abf25d0836d58a666b91d61b99bf80</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Merge AArch64 libcpu and add some drivers for their bsps</title>
<updated>2021-09-26T07:01:59Z</updated>
<author>
<name>GuEe-GUI</name>
<email>2991707448@qq.com</email>
</author>
<published>2021-09-22T09:57:45Z</published>
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<id>urn:sha1:740cd9dfb013a26cb5a9106a717deedd4478eff5</id>
<content type='text'>
</content>
</entry>
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