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<title>rt-thread.git/libcpu/aarch64/common/trap.c, branch v5.0.2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/rt-thread.git/atom/libcpu/aarch64/common/trap.c?h=v5.0.2</id>
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<updated>2023-09-11T06:05:41Z</updated>
<entry>
<title>change aarch64 trap backtrace &amp; coredump priority rating. (#8008)</title>
<updated>2023-09-11T06:05:41Z</updated>
<author>
<name>geniusgogo</name>
<email>2041245+geniusgogo@users.noreply.github.com</email>
</author>
<published>2023-09-11T06:05:41Z</published>
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<id>urn:sha1:e8e980879e7471ef27220a3ecddf65e982622205</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[smart/syscall] fix exit(2) and add exit_group(2) (#8005)</title>
<updated>2023-09-09T01:35:56Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-09-09T01:35:56Z</published>
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<id>urn:sha1:47b183a2978a8b474e25ec38b37ef5741a50d724</id>
<content type='text'>
Signed-off-by: shell &lt;smokewood@qq.com&gt;
Signed-off-by: shell &lt;wangxiaoyao@rt-thread.com&gt;
Signed-off-by: Shell &lt;smokewood@qq.com&gt;</content>
</entry>
<entry>
<title>[components/mm] add unmap page API (#7834)</title>
<updated>2023-08-16T07:38:59Z</updated>
<author>
<name>Shell</name>
<email>smokewood@qq.com</email>
</author>
<published>2023-08-16T07:38:59Z</published>
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<id>urn:sha1:d862816a51ab6fec2321f0410e8aea2d05507542</id>
<content type='text'>
Signed-off-by: Shell &lt;smokewood@qq.com&gt;</content>
</entry>
<entry>
<title>update components &amp; lwp. (#7888)</title>
<updated>2023-08-07T16:22:14Z</updated>
<author>
<name>geniusgogo</name>
<email>2041245+geniusgogo@users.noreply.github.com</email>
</author>
<published>2023-08-07T16:22:14Z</published>
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<id>urn:sha1:4d20416b2f62cbb6c98e88223d6a0d1638b7f1c0</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[kernel] 将rt_thread结构体改为显式继承rt_object (#7131)</title>
<updated>2023-04-04T13:06:27Z</updated>
<author>
<name>Shicheng Chu</name>
<email>1468559561@qq.com</email>
</author>
<published>2023-04-04T13:06:27Z</published>
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<id>urn:sha1:93f3cb30e48d5de341bda09fa806120e2bc3f3ad</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[rt-smart] testcase &amp; improvements for memory management (#7099)</title>
<updated>2023-03-30T00:25:15Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-03-30T00:25:15Z</published>
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<id>urn:sha1:eec78d9f5d3f0a944500a1cac5802dfee2befc7b</id>
<content type='text'>
* [utest/mm] add testcase for create/init
format codes of create/init in components/mm

* [libcpu/aarch64] fix user stack check routine

* [kservice] export API for utest

* [utest/mm] testcase for aspace_map
format &amp; modify the files under components/mm related with aspace_map

* [lwp/user_mm] add user_map_varea for mmap feature

* [mm] rename rt_mm_fault_try_fix to rt_aspace_fault_try_fix

* [utest/mm] testcase for synchronization

* [mm] modify unmap api to improve throughput

* [utest/mm] testcases for cache and varea map

* [format] remove extra space

* [utest/mm] fix testcase problem in header

* [lwp] extend map_user_varea with a flag

* [utest/mm] testcase for lwp_map_user_varea

* [libcpu/arm/cortex-a] fix kernel space layout

* [utest/mm] adjust for armv7 arch</content>
</entry>
<entry>
<title>[rt-smart] PV_OFFSET as a variable (#6904)</title>
<updated>2023-02-14T15:08:32Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-02-14T15:08:32Z</published>
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<id>urn:sha1:2d0974908659bd41d748e69fac0166c37b15cb02</id>
<content type='text'>
* [rt-smart/mem] remove pv_offset

* [rt-smart] list kernel space command

* [rt-smart] restore ioremap region

* [revert] restore kernel space isolation

* [rt-smart/pv_off] code format

* [rt-smart] add get_pvoff()

* [pvoffset] pvoff as constant for C codes

* [pvoff] pvoff as interfaces</content>
</entry>
<entry>
<title>[rt-smart] kernel virtual memory management layer (#6809)</title>
<updated>2023-01-09T02:08:55Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-01-09T02:08:55Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=7450ef6c4d71f992444d27f4a26c16f813ed8e55'/>
<id>urn:sha1:7450ef6c4d71f992444d27f4a26c16f813ed8e55</id>
<content type='text'>
synchronize virtual memory system works.
adding kernel virtual memory management layer for page-based MMU enabled architecture
porting libcpu MMU codes
porting lwp memory related codes</content>
</entry>
<entry>
<title>[smart/aarch64] code sync (#6750)</title>
<updated>2022-12-20T09:49:37Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2022-12-20T09:49:37Z</published>
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<id>urn:sha1:e8504c7cf1d03c07608e2197eaef728a6aecde7a</id>
<content type='text'>
* [smart/aarch64] sync aarch64</content>
</entry>
<entry>
<title>[libcpu/aarch64] rt_hw_trap_irq get irq instead of iar when using gicv2 (#5601)</title>
<updated>2022-02-16T17:00:29Z</updated>
<author>
<name>GUI</name>
<email>39894654+GuEe-GUI@users.noreply.github.com</email>
</author>
<published>2022-02-16T17:00:29Z</published>
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<id>urn:sha1:85dc9bd4a6e798c74f16a87bc91191907dfdbaf7</id>
<content type='text'>
* [libcpu/aarch64] add smp support
* [libcpu/aarch64] rt_hw_trap_irq get irq instead of iar when using gicv2</content>
</entry>
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