rt-thread.git/libcpu/aarch64/common, branch v5.2.1-beta

libcpu: aarch64: Fix NORMAL_NOCACHE_MEM attr (#10180)

2025-04-13T14:12:00Z

Signed-off-by: Cliff Chen Signed-off-by: mouch6131 <187177037@qq.com> Co-authored-by: Cliff Chen

libcpu: cleanup undefined rt_hw_mmu_kernel_map_init (#10177)

2025-04-10T23:54:21Z

* libcpu: cleanup undefined rt_hw_mmu_kernel_map_init rt_hw_mmu_kernel_map_init() is declared in header files but no definition found, cleanup the code. Signed-off-by: Chen Wang * bsp: allwinner: d1: remove calling of rt_hw_mmu_kernel_map_init rt_hw_mmu_kernel_map_init is an undefined function, calling it is meaningless. Signed-off-by: Chen Wang --------- Signed-off-by: Chen Wang

[libcpu][aarch64]fix gicv3 mpidr table (#9284)

2025-03-28T03:08:28Z

* fix gicv3 mpidr error * phytium should support rt_cpu_mpidr_table by using common_setup

feat: mm: added affinity pages allocator

2025-02-25T03:26:30Z

This patch introduces a tagged pages allocator to address the existing problems of page aliasing on specific platforms and the requirement of page coloring. It implements an affinity-id aware page manager by separating the runtime page list into two types: a normal single linked-list and a multi-dimensional affinity-list. Changes: - Introduced tagged pages allocator and managing algorithm for affinity pages list - Modified components to support affinity-id list management - Updated page allocation and freeing functions to handle tagged pages - Added configuration options for page affinity block size and debugging - Modified mmap and elf loading to respect affinity settings - Enhanced page list management to support multi-dimensional affinity-list Signed-off-by: Shell

feat: arm64: mmu: auto-sensing of best paging stride

2024-12-14T04:38:32Z

Improves the memory mapping process by dynamically selecting the optimal paging stride (4K or 2M) based on virtual address alignment and mapping size. This eliminates the need for upfront stride determination, enhancing flexibility and maintainability in memory management. Changes: - Replaced fixed stride selection logic with a dynamic decision loop. - Removed `npages` calculation and replaced with `remaining_sz` to track unprocessed memory size. - Added assertions to ensure `size` is properly aligned to the smallest page size. - Adjusted loop to dynamically determine and apply the appropriate stride (4K or 2M) for each mapping iteration. - Updated virtual and physical address increments to use the dynamically selected stride. Signed-off-by: Shell

[FIXUP] __rt_clz loss in aarch64

2024-12-13T02:39:20Z

Signed-off-by: GuEe-GUI <2991707448@qq.com>

feat: arm64 ASID support

2024-11-24T18:44:34Z

Support for ARM64 ASID to enhance virtual memory management efficiency by reducing the need for TLB flushes during address space switches. These changes improve performance especially for multi-process systems. Changes: - Added `ARCH_USING_ASID` configuration in `libcpu/aarch64/Kconfig`. - Defined ASID-related constants in `mmu.h`. - Updated `TLBI_ARG` macro to include ASID manipulation. - Implemented ASID allocation mechanism with spinlock synchronization. - Enhanced TLB invalidation to support ASID-specific operations. - Modified `rt_hw_aspace_switch` to use ASIDs when switching address spaces. - Adjusted debug logging and function documentation to reflect ASID usage. - Refactored AArch64 MMU and TLB handling for ASID integration. Signed-off-by: Shell

[DM/FIXUP] remove some redundant INIT_EXPORT

2024-11-18T07:03:23Z

Signed-off-by: GuEe-GUI <2991707448@qq.com>

[libcpu] fix No memory higher than 1 GB is mapped

2024-11-18T02:13:07Z

[libcpu] fix No memory higher than 1 GB is mapped

2024-11-18T02:13:07Z