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<title>rt-thread.git/libcpu/aarch64, branch master</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/rt-thread.git/atom/libcpu/aarch64?h=master</id>
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<updated>2026-08-16T11:56:03Z</updated>
<entry>
<title>[bsp/raspberry-pi] update DM support</title>
<updated>2026-08-16T11:56:03Z</updated>
<author>
<name>GuEe-GUI</name>
<email>2991707448@qq.com</email>
</author>
<published>2026-08-15T14:36:46Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=f7258a6bb80d9be12e73675ab35a04651e32eda3'/>
<id>urn:sha1:f7258a6bb80d9be12e73675ab35a04651e32eda3</id>
<content type='text'>
- reorganize common Raspberry Pi drivers under the device framework
- add the Raspberry Pi 5 BSP, configuration and documentation
- add BCM2712 and DesignWare AXI DMA controller support
- distinguish BCM2712 DMA32 and DMA40 channels by channel mask
- restore DesignWare AXI DMA enable bits after controller reset
- support a shared AXI maximum burst length across DMA channels

Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;
</content>
</entry>
<entry>
<title>[dm][dma] Update DMA (#11678)</title>
<updated>2026-08-14T04:42:01Z</updated>
<author>
<name>GUI</name>
<email>39894654+GuEe-GUI@users.noreply.github.com</email>
</author>
<published>2026-08-14T04:42:01Z</published>
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<id>urn:sha1:f2c05253d11f0b5746ade4bdb7d8d838bb7a5df1</id>
<content type='text'>
* [dm][dma] update DMA interface

Extend DMA mapping to honor OFW dma-ranges even
when no reserved memory pool is present,
and add PCI host-bridge DMA-region translation for PCI devices.
Prefer 32-bit-addressable allocations for translated devices,
improve pool allocation fallbacks and synchronization,
and establish a linear mapping for installed DMA pools when possible.

Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;

* [dm][dma] fixup PL330 work flow

Fix PL330 channel allocation so device-tree cells
select peripheral request lines rather than execution channels.
Generate proper peripheral DMA microcode using DMAWFP, DMALDP, DMASTP, and DMAFLUSHP,
encode burst lengths correctly,
honor transfer direction and non-secure attributes,
and allocate microcode from DMA-coherent memory.

Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;

* style: format code with clang-format

* style: format complete changed files with clang-format

* drivers: dma: fix diagnostic format types

* style: format DMA changes for current master

---------

Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;</content>
</entry>
<entry>
<title>Fix:Always use vmalle1is for kernel aspace; only use aside1is for user aspace with non-global PTE.</title>
<updated>2026-06-26T09:54:38Z</updated>
<author>
<name>run.mao</name>
<email>1406108610@qq.com</email>
</author>
<published>2026-06-17T08:17:49Z</published>
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<id>urn:sha1:187dc3fddfe45202f4c1000a724f38cdc742dd2e</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[libcpu][aarch64] support DVFS idle</title>
<updated>2026-06-23T00:02:09Z</updated>
<author>
<name>GuEe-GUI</name>
<email>2991707448@qq.com</email>
</author>
<published>2026-06-15T07:35:26Z</published>
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<id>urn:sha1:741d82c42b1ae96fe3634be4469fb2f33def2df7</id>
<content type='text'>
Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;
</content>
</entry>
<entry>
<title>[bsp][zynqmp-a53-dfzu2eg] enable full dm</title>
<updated>2026-06-08T06:57:37Z</updated>
<author>
<name>GuEe-GUI</name>
<email>2991707448@qq.com</email>
</author>
<published>2026-03-06T13:10:56Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=63965cb103e5dcc6fe253579a063019542bdb35c'/>
<id>urn:sha1:63965cb103e5dcc6fe253579a063019542bdb35c</id>
<content type='text'>
This is a builtin fdt example BSP

Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;
</content>
</entry>
<entry>
<title>[components][clock_time] Refactor time subsystem around clock_time (#11111)</title>
<updated>2026-01-31T09:44:27Z</updated>
<author>
<name>Bernard Xiong</name>
<email>bernard.xiong@gmail.com</email>
</author>
<published>2026-01-31T09:44:27Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=743b614875fc33257be47ab53b6c5e040ec27893'/>
<id>urn:sha1:743b614875fc33257be47ab53b6c5e040ec27893</id>
<content type='text'>
* [components][clock_time] Refactor time subsystem around clock_time

Introduce the clock_time core with clock source/event separation, high-resolution scheduling, and boot-time helpers, plus clock_timer adapters for timer peripherals.

Remove legacy ktime/cputime/hwtimer implementations and migrate arch and BSP time paths to the new subsystem while keeping POSIX time integration functional.

Update drivers, Kconfig/SConscript wiring, documentation, and tests; add clock_time overview docs and align naming to clock_boottime/clock_hrtimer/clock_timer.

* [components][clock_time] Use BSP-provided clock timer frequency on riscv64

* [risc-v] Use runtime clock timer frequency for tick and delays

* [bsp] Add clock timer frequency hooks for riscv64 boards

* [bsp] Update Renesas RA driver doc clock_timer link

* [bsp] Sync zynqmp-r5-axu4ev rtconfig after config refresh

* [bsp][rk3500] Update rk3500 clock configuration

* [bsp][hpmicro] Add rt_hw_us_delay hook and update board delays

* [bsp][stm32l496-st-nucleo] enable clock_time for hwtimer sample in ci

* [bsp][hpmicro] Fix rtconfig include scope for hpm6750evk

Move rtconfig.h include outside the ENET_MULTIPLE_PORT guard for hpm6750evk and hpm6750evk2 so configuration macros are available regardless of ENET settings.

* [bsp][raspi3] select clock time for systimer

* [bsp][hpm5300evk] Trim trailing blank line

* [bsp][hpm5301evklite] Trim trailing blank line

* [bsp][hpm5e00evk] Trim trailing blank line

* [bsp][hpm6200evk] Trim trailing blank line

* [bsp][hpm6300evk] Trim trailing blank line

* [bsp][hpm6750evk] Trim trailing blank line

* [bsp][hpm6750evk2] Trim trailing blank line

* [bsp][hpm6750evkmini] Trim trailing blank line

* [bsp][hpm6800evk] Trim trailing blank line

* [bsp][hpm6e00evk] Trim trailing blank line

* [bsp][nxp] switch lpc178x to gcc and remove mcx timer source

* [bsp][stm32] fix the CONFIG_RT_USING_CLOCK_TIME issue.

* [docs][clock_time] add clock time documentation

* [docs][clock_time] Update clock time subsystem documentation

- Update device driver index to use correct page reference
- Clarify upper layer responsibilities in architecture overview
- Update README to describe POSIX/libc, Soft RTC, and device driver usage
- Refine architecture diagram with improved layout and color scheme
- Remove obsolete clock_timer.md file

* [kernel][utest] Trim trailing space

* [clock_time] Fix hrtimer wrap handling

* [clock_time] fix the static rt_inline issue

* [clock_time] fix the rt_clock_hrtimer_control result issue</content>
</entry>
<entry>
<title>[libcpu][aarch64] Replace x8 with a callee-saved register</title>
<updated>2026-01-13T05:42:26Z</updated>
<author>
<name>Tang Qingmei</name>
<email>qingmeytang@163.com</email>
</author>
<published>2025-12-27T14:17:43Z</published>
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<id>urn:sha1:6c2b9a8f20c4524d796312016242d4362eeb5796</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[libcpu][aarch64] Update for DM</title>
<updated>2025-12-19T13:18:54Z</updated>
<author>
<name>GuEe-GUI</name>
<email>2991707448@qq.com</email>
</author>
<published>2025-12-17T07:11:39Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=77fbed5744872a825ce71222796b9bdcee30526c'/>
<id>urn:sha1:77fbed5744872a825ce71222796b9bdcee30526c</id>
<content type='text'>
1. PSCI port to system power.
2. Support builtin fdt.
3. Update system aspace size.
4. Support DMA memory probe.
5. Fixup not backtrace in Serror for device bus fault.

Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;
</content>
</entry>
<entry>
<title>Reorganize Group names in build system for clarity and IDE integration #10923</title>
<updated>2025-11-16T03:40:53Z</updated>
<author>
<name>Copilot</name>
<email>198982749+Copilot@users.noreply.github.com</email>
</author>
<published>2025-11-16T03:40:53Z</published>
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<id>urn:sha1:30e1e5e9dcdaff17258edf70b9f9783e08356288</id>
<content type='text'>
</content>
</entry>
<entry>
<title>aarch64: document the CNTFRQ_EL0</title>
<updated>2025-10-23T14:08:05Z</updated>
<author>
<name>Yonggang Luo</name>
<email>luoyonggang@gmail.com</email>
</author>
<published>2025-10-21T07:53:14Z</published>
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<id>urn:sha1:0cf096e0645746aa18eacb01725a71373a574516</id>
<content type='text'>
Signed-off-by: Yonggang Luo &lt;luoyonggang@gmail.com&gt;
</content>
</entry>
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