rt-thread.git/libcpu/aarch64, branch v5.2.1

import re

2025-04-28T02:52:58Z

Fix Aarch64 architecture runtime issues

2025-04-28T02:52:58Z

该问题由5b3320624da5149fc21c2d3e1f321d855e3d0dfe引入，导致工具链编译时加上了 -std=gnu99,其他架构是否出问题暂时未知

libcpu: aarch64: Fix NORMAL_NOCACHE_MEM attr (#10180)

2025-04-13T14:12:00Z

Signed-off-by: Cliff Chen Signed-off-by: mouch6131 <187177037@qq.com> Co-authored-by: Cliff Chen

libcpu: cleanup undefined rt_hw_mmu_kernel_map_init (#10177)

2025-04-10T23:54:21Z

* libcpu: cleanup undefined rt_hw_mmu_kernel_map_init rt_hw_mmu_kernel_map_init() is declared in header files but no definition found, cleanup the code. Signed-off-by: Chen Wang * bsp: allwinner: d1: remove calling of rt_hw_mmu_kernel_map_init rt_hw_mmu_kernel_map_init is an undefined function, calling it is meaningless. Signed-off-by: Chen Wang --------- Signed-off-by: Chen Wang

[libcpu][aarch64]fix gicv3 mpidr table (#9284)

2025-03-28T03:08:28Z

* fix gicv3 mpidr error * phytium should support rt_cpu_mpidr_table by using common_setup

feat: mm: added affinity pages allocator

2025-02-25T03:26:30Z

This patch introduces a tagged pages allocator to address the existing problems of page aliasing on specific platforms and the requirement of page coloring. It implements an affinity-id aware page manager by separating the runtime page list into two types: a normal single linked-list and a multi-dimensional affinity-list. Changes: - Introduced tagged pages allocator and managing algorithm for affinity pages list - Modified components to support affinity-id list management - Updated page allocation and freeing functions to handle tagged pages - Added configuration options for page affinity block size and debugging - Modified mmap and elf loading to respect affinity settings - Enhanced page list management to support multi-dimensional affinity-list Signed-off-by: Shell

[AARCH64] Update kernel's boot link for ARM64

2025-02-11T06:58:18Z

Signed-off-by: GuEe-GUI <2991707448@qq.com>

feat: arm64: mmu: auto-sensing of best paging stride

2024-12-14T04:38:32Z

Improves the memory mapping process by dynamically selecting the optimal paging stride (4K or 2M) based on virtual address alignment and mapping size. This eliminates the need for upfront stride determination, enhancing flexibility and maintainability in memory management. Changes: - Replaced fixed stride selection logic with a dynamic decision loop. - Removed `npages` calculation and replaced with `remaining_sz` to track unprocessed memory size. - Added assertions to ensure `size` is properly aligned to the smallest page size. - Adjusted loop to dynamically determine and apply the appropriate stride (4K or 2M) for each mapping iteration. - Updated virtual and physical address increments to use the dynamically selected stride. Signed-off-by: Shell

[FIXUP] __rt_clz loss in aarch64

2024-12-13T02:39:20Z

Signed-off-by: GuEe-GUI <2991707448@qq.com>

feat: Kconfig: moving the arm64 specified configs to sub-menu

2024-11-24T18:44:34Z

Just for better readability. Signed-off-by: Shell