rt-thread.git/libcpu/arm/cortex-a/cache.c, branch serialX-dev Unnamed repository; edit this file 'description' to name the repository. http://cgit.235523.xyz/rt-thread.git/atom/libcpu/arm/cortex-a/cache.c?h=serialX-dev 2022-12-16T10:38:28Z [rt-smart] 弱化 RT_USING_LWP，使用 RT_USING_SMART 作为宏配置 (#6740) 2022-12-16T10:38:28Z guo guozhanxin@rt-thread.com 2022-12-16T10:38:28Z urn:sha1:68ca9f07a60ad5cbe52b37b52299327b6246e7f7 * [dfs] sync cromfs * [rt-smart]Weaken RT_USING_LWP, use RT_USING_SMART as macro configuration * [format] fix some format issue. sync branch rt-smart. (#6641) 2022-12-03T04:07:44Z guo guozhanxin@rt-thread.com 2022-12-03T04:07:44Z urn:sha1:ecf2d8215961ca7c539132b62a72df6072cc3e14 * Synchronize the code of the rt mart branch to the master branch. * TTY device * Add lwP code from rt-smart * Add vnode in DFS, but DFS will be re-write for rt-smart * There are three libcpu for rt-smart: * arm/cortex-a, arm/aarch64 * riscv64 Co-authored-by: Rbb666 <zhangbingru@rt-thread.com> Co-authored-by: zhkag <zhkag@foxmail.com> 添加dcache invalidate/dcache clean&invalidate接口 2021-07-03T09:34:45Z fenghuijie fenghuijie1990@163.com 2021-07-03T09:34:45Z urn:sha1:da701d6b3a7b28d7dd2aca4897a902476b1581e4 [libcpu] auto formatted 2021-03-27T09:51:56Z Meco Man 920369182@qq.com 2021-03-27T09:51:56Z urn:sha1:6c907c3a477b1f34ca1adb277748c3306110cabf fix cortex-a cahce 2019-06-19T02:40:13Z ZYH lymz@foxmail.com 2019-06-19T02:29:56Z urn:sha1:fc155f88107ca347fb2d306793476786e544f993 Add standard rt-thread cache interfaces for arm/cortex-a. 2019-03-29T12:22:25Z qz721 295354721@qq.com 2019-03-29T12:22:25Z urn:sha1:fbd40fc5b8b94cf370fdea9a2433991f43e542f6 Add cache invalidate and clean interfaces. Adjust the default cache type of memory to 'WriteBach with WriteAllocate'.