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<title>rt-thread.git/libcpu/arm/cortex-a/context_gcc.S, branch v5.2.2-beta</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/rt-thread.git/atom/libcpu/arm/cortex-a/context_gcc.S?h=v5.2.2-beta</id>
<link rel='self' href='http://cgit.235523.xyz/rt-thread.git/atom/libcpu/arm/cortex-a/context_gcc.S?h=v5.2.2-beta'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/'/>
<updated>2023-07-25T06:07:44Z</updated>
<entry>
<title>[libcpu/arm] fix race condition with ldrex,strex (#7842)</title>
<updated>2023-07-25T06:07:44Z</updated>
<author>
<name>Shell</name>
<email>smokewood@qq.com</email>
</author>
<published>2023-07-25T06:07:44Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=acfa74f078b23d670ad04c3a2aa9cec5fbcf5afe'/>
<id>urn:sha1:acfa74f078b23d670ad04c3a2aa9cec5fbcf5afe</id>
<content type='text'>
Signed-off-by: Shell &lt;smokewood@qq.com&gt;</content>
</entry>
<entry>
<title>[rt-smart] kernel virtual memory management layer (#6809)</title>
<updated>2023-01-09T02:08:55Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-01-09T02:08:55Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=7450ef6c4d71f992444d27f4a26c16f813ed8e55'/>
<id>urn:sha1:7450ef6c4d71f992444d27f4a26c16f813ed8e55</id>
<content type='text'>
synchronize virtual memory system works.
adding kernel virtual memory management layer for page-based MMU enabled architecture
porting libcpu MMU codes
porting lwp memory related codes</content>
</entry>
<entry>
<title>[rt-smart] 弱化 RT_USING_LWP，使用 RT_USING_SMART 作为宏配置 (#6740)</title>
<updated>2022-12-16T10:38:28Z</updated>
<author>
<name>guo</name>
<email>guozhanxin@rt-thread.com</email>
</author>
<published>2022-12-16T10:38:28Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=68ca9f07a60ad5cbe52b37b52299327b6246e7f7'/>
<id>urn:sha1:68ca9f07a60ad5cbe52b37b52299327b6246e7f7</id>
<content type='text'>
* [dfs] sync cromfs

* [rt-smart]Weaken RT_USING_LWP, use RT_USING_SMART as macro configuration

* [format] fix some format issue.</content>
</entry>
<entry>
<title>sync branch rt-smart. (#6641)</title>
<updated>2022-12-03T04:07:44Z</updated>
<author>
<name>guo</name>
<email>guozhanxin@rt-thread.com</email>
</author>
<published>2022-12-03T04:07:44Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=ecf2d8215961ca7c539132b62a72df6072cc3e14'/>
<id>urn:sha1:ecf2d8215961ca7c539132b62a72df6072cc3e14</id>
<content type='text'>
* Synchronize the code of the rt mart branch to the master branch.
  * TTY device
  * Add lwP code from rt-smart
  * Add vnode in DFS, but DFS will be re-write for rt-smart
  * There are three libcpu for rt-smart:
    * arm/cortex-a, arm/aarch64
    * riscv64

Co-authored-by: Rbb666 &lt;zhangbingru@rt-thread.com&gt;
Co-authored-by: zhkag &lt;zhkag@foxmail.com&gt;</content>
</entry>
<entry>
<title>add cortex-a fpu support</title>
<updated>2019-05-29T00:40:41Z</updated>
<author>
<name>shaojinchun</name>
<email>shaojinchun@rt-thread.com</email>
</author>
<published>2019-05-29T00:26:08Z</published>
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<id>urn:sha1:043611b98aca955e9cb511c51baf7240389fba75</id>
<content type='text'>
</content>
</entry>
<entry>
<title>fix signal code</title>
<updated>2019-05-11T01:34:26Z</updated>
<author>
<name>shaojinchun</name>
<email>shaojinchun@rt-thread.com</email>
</author>
<published>2019-05-09T11:28:52Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=6cdfb2ac92d8422136f926024b2c2f969fce6b9e'/>
<id>urn:sha1:6cdfb2ac92d8422136f926024b2c2f969fce6b9e</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[libcpu][arm/cortex-a] Add correct comments.</title>
<updated>2019-05-09T00:48:38Z</updated>
<author>
<name>Bernard Xiong</name>
<email>bernard.xiong@gmail.com</email>
</author>
<published>2019-05-09T00:39:08Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=d729448f5e84b96eaede631cab5201c21bfe24e1'/>
<id>urn:sha1:d729448f5e84b96eaede631cab5201c21bfe24e1</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Make 'qemu-vexpress-a9' and 'imx6ul' use the same libcpu code.</title>
<updated>2019-03-25T12:03:49Z</updated>
<author>
<name>qz721</name>
<email>295354721@qq.com</email>
</author>
<published>2019-03-25T12:03:49Z</published>
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<id>urn:sha1:2eb1bef773e099ac93ec74dba7ec216bdf61597c</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[license] Change the license of libarm to Apache.</title>
<updated>2018-10-14T17:35:07Z</updated>
<author>
<name>Bernard Xiong</name>
<email>bernard.xiong@gmail.com</email>
</author>
<published>2018-10-14T17:35:07Z</published>
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<id>urn:sha1:7c425408b4335d7af2fefcfa51174735b98037ed</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[BSP] add i.MX 6UL BSP</title>
<updated>2017-11-01T05:30:17Z</updated>
<author>
<name>Bernard Xiong</name>
<email>bernard.xiong@gmail.com</email>
</author>
<published>2017-11-01T05:30:17Z</published>
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<id>urn:sha1:f6170a6e5bbfe073d05e2b741eb6883946704f44</id>
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</content>
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