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<title>rt-thread.git/libcpu/arm/cortex-a/trap.c, branch v5.0.1</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/rt-thread.git/atom/libcpu/arm/cortex-a/trap.c?h=v5.0.1</id>
<link rel='self' href='http://cgit.235523.xyz/rt-thread.git/atom/libcpu/arm/cortex-a/trap.c?h=v5.0.1'/>
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<updated>2023-03-30T00:25:15Z</updated>
<entry>
<title>[rt-smart] testcase &amp; improvements for memory management (#7099)</title>
<updated>2023-03-30T00:25:15Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-03-30T00:25:15Z</published>
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<id>urn:sha1:eec78d9f5d3f0a944500a1cac5802dfee2befc7b</id>
<content type='text'>
* [utest/mm] add testcase for create/init
format codes of create/init in components/mm

* [libcpu/aarch64] fix user stack check routine

* [kservice] export API for utest

* [utest/mm] testcase for aspace_map
format &amp; modify the files under components/mm related with aspace_map

* [lwp/user_mm] add user_map_varea for mmap feature

* [mm] rename rt_mm_fault_try_fix to rt_aspace_fault_try_fix

* [utest/mm] testcase for synchronization

* [mm] modify unmap api to improve throughput

* [utest/mm] testcases for cache and varea map

* [format] remove extra space

* [utest/mm] fix testcase problem in header

* [lwp] extend map_user_varea with a flag

* [utest/mm] testcase for lwp_map_user_varea

* [libcpu/arm/cortex-a] fix kernel space layout

* [utest/mm] adjust for armv7 arch</content>
</entry>
<entry>
<title>[rt-smart] kernel virtual memory management layer (#6809)</title>
<updated>2023-01-09T02:08:55Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-01-09T02:08:55Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=7450ef6c4d71f992444d27f4a26c16f813ed8e55'/>
<id>urn:sha1:7450ef6c4d71f992444d27f4a26c16f813ed8e55</id>
<content type='text'>
synchronize virtual memory system works.
adding kernel virtual memory management layer for page-based MMU enabled architecture
porting libcpu MMU codes
porting lwp memory related codes</content>
</entry>
<entry>
<title>[rt-smart] 弱化 RT_USING_LWP，使用 RT_USING_SMART 作为宏配置 (#6740)</title>
<updated>2022-12-16T10:38:28Z</updated>
<author>
<name>guo</name>
<email>guozhanxin@rt-thread.com</email>
</author>
<published>2022-12-16T10:38:28Z</published>
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<id>urn:sha1:68ca9f07a60ad5cbe52b37b52299327b6246e7f7</id>
<content type='text'>
* [dfs] sync cromfs

* [rt-smart]Weaken RT_USING_LWP, use RT_USING_SMART as macro configuration

* [format] fix some format issue.</content>
</entry>
<entry>
<title>sync branch rt-smart. (#6641)</title>
<updated>2022-12-03T04:07:44Z</updated>
<author>
<name>guo</name>
<email>guozhanxin@rt-thread.com</email>
</author>
<published>2022-12-03T04:07:44Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=ecf2d8215961ca7c539132b62a72df6072cc3e14'/>
<id>urn:sha1:ecf2d8215961ca7c539132b62a72df6072cc3e14</id>
<content type='text'>
* Synchronize the code of the rt mart branch to the master branch.
  * TTY device
  * Add lwP code from rt-smart
  * Add vnode in DFS, but DFS will be re-write for rt-smart
  * There are three libcpu for rt-smart:
    * arm/cortex-a, arm/aarch64
    * riscv64

Co-authored-by: Rbb666 &lt;zhangbingru@rt-thread.com&gt;
Co-authored-by: zhkag &lt;zhkag@foxmail.com&gt;</content>
</entry>
<entry>
<title>[libcpu][arm] Add exception install function (#5827)</title>
<updated>2022-04-23T17:03:54Z</updated>
<author>
<name>Tangyuxin</name>
<email>462747508@qq.com</email>
</author>
<published>2022-04-23T17:03:54Z</published>
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<id>urn:sha1:c80993f71328876a467a966563a4b6c11f8f2243</id>
<content type='text'>
</content>
</entry>
<entry>
<title>FINSH_USING_BUILT_IN_COMMANDS改MSH_USING_BUILT_IN_COMMANDS</title>
<updated>2021-08-28T20:48:08Z</updated>
<author>
<name>Meco Man</name>
<email>920369182@qq.com</email>
</author>
<published>2021-08-28T20:48:08Z</published>
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<id>urn:sha1:1997113fbca8894dcaad75a6fa4e7b42396a4031</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[finsh] finsh组件可以选择是否包含内置命令</title>
<updated>2021-08-25T23:48:15Z</updated>
<author>
<name>Meco Man</name>
<email>920369182@qq.com</email>
</author>
<published>2021-08-25T23:10:01Z</published>
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<id>urn:sha1:29828dc94fb55b1224dd0b7a31b388a11fe51870</id>
<content type='text'>
</content>
</entry>
<entry>
<title>调整异常处理代码结构，以支持backtrace功能</title>
<updated>2021-07-05T06:43:33Z</updated>
<author>
<name>fenghuijie</name>
<email>fenghuijie1990@163.com</email>
</author>
<published>2021-07-05T06:43:33Z</published>
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<id>urn:sha1:e933c1f6105caf4e68bd57bc5521767b32063a5f</id>
<content type='text'>
</content>
</entry>
<entry>
<title>修改irq handle接口rt_hw_trap_irq，支持核间IPI中断处理</title>
<updated>2021-07-05T06:06:32Z</updated>
<author>
<name>fenghuijie</name>
<email>fenghuijie1990@163.com</email>
</author>
<published>2021-07-05T06:06:32Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=eb79a8a244d3d90665df0a5f3289f90bd1f9aeb1'/>
<id>urn:sha1:eb79a8a244d3d90665df0a5f3289f90bd1f9aeb1</id>
<content type='text'>
</content>
</entry>
<entry>
<title>优化未定义异常时自动开启FPU的判断条件，当FPU末开启时将自动开启。</title>
<updated>2021-04-08T02:01:26Z</updated>
<author>
<name>zhouji</name>
<email>956133287@qq.com</email>
</author>
<published>2021-04-06T11:15:02Z</published>
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<id>urn:sha1:e939ffe35502b2c0ccfa709673b21a42d2253109</id>
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