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<title>rt-thread.git/libcpu/arm/cortex-a, branch v4.0.1</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/rt-thread.git/atom/libcpu/arm/cortex-a?h=v4.0.1</id>
<link rel='self' href='http://cgit.235523.xyz/rt-thread.git/atom/libcpu/arm/cortex-a?h=v4.0.1'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/'/>
<updated>2019-05-12T07:07:26Z</updated>
<entry>
<title>[BSP][qemu-vexpress-a9] code cleaup for compiling warning.</title>
<updated>2019-05-12T07:07:26Z</updated>
<author>
<name>Bernard Xiong</name>
<email>bernard.xiong@gmail.com</email>
</author>
<published>2019-05-12T07:07:26Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=ec6cb9f2602c11a676b059c8f23401422690227c'/>
<id>urn:sha1:ec6cb9f2602c11a676b059c8f23401422690227c</id>
<content type='text'>
</content>
</entry>
<entry>
<title>fix signal code</title>
<updated>2019-05-11T01:34:26Z</updated>
<author>
<name>shaojinchun</name>
<email>shaojinchun@rt-thread.com</email>
</author>
<published>2019-05-09T11:28:52Z</published>
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<id>urn:sha1:6cdfb2ac92d8422136f926024b2c2f969fce6b9e</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[libcpu][arm/cortex-a] Add correct comments.</title>
<updated>2019-05-09T00:48:38Z</updated>
<author>
<name>Bernard Xiong</name>
<email>bernard.xiong@gmail.com</email>
</author>
<published>2019-05-09T00:39:08Z</published>
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<id>urn:sha1:d729448f5e84b96eaede631cab5201c21bfe24e1</id>
<content type='text'>
</content>
</entry>
<entry>
<title>修改lwp支持中arm cortex-a的swi入口函数处理</title>
<updated>2019-04-27T05:54:51Z</updated>
<author>
<name>shaojinchun</name>
<email>shaojinchun@rt-thread.com</email>
</author>
<published>2019-04-27T05:54:51Z</published>
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<id>urn:sha1:1e7bd3d8a1082060f6cf71631849da903787d045</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Rename 'platform.h' in 'imx6ul' and 'qemu-vexpress-a9' BSPs.</title>
<updated>2019-04-26T02:50:48Z</updated>
<author>
<name>qz721</name>
<email>295354721@qq.com</email>
</author>
<published>2019-04-26T02:50:48Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=61f2a71511121bf48949a6f3df9cd4089410b003'/>
<id>urn:sha1:61f2a71511121bf48949a6f3df9cd4089410b003</id>
<content type='text'>
This filename conflicts with the 'mbedtls' package. They are renamed
in the name of the corresponding chips and included in 'board.h'.
Files that rely on this file should include 'board.h' instead.
</content>
</entry>
<entry>
<title>Disable the data alignment check.</title>
<updated>2019-04-01T06:21:59Z</updated>
<author>
<name>qz721</name>
<email>295354721@qq.com</email>
</author>
<published>2019-04-01T06:21:59Z</published>
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<id>urn:sha1:b10039f396cb1f32cb0a4b7ee3692bf96332fc1e</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Add standard rt-thread cache interfaces for arm/cortex-a.</title>
<updated>2019-03-29T12:22:25Z</updated>
<author>
<name>qz721</name>
<email>295354721@qq.com</email>
</author>
<published>2019-03-29T12:22:25Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=fbd40fc5b8b94cf370fdea9a2433991f43e542f6'/>
<id>urn:sha1:fbd40fc5b8b94cf370fdea9a2433991f43e542f6</id>
<content type='text'>
Add cache invalidate and clean interfaces.
Adjust the default cache type of memory to 'WriteBach with WriteAllocate'.
</content>
</entry>
<entry>
<title>Make 'qemu-vexpress-a9' and 'imx6ul' use the same libcpu code.</title>
<updated>2019-03-25T12:03:49Z</updated>
<author>
<name>qz721</name>
<email>295354721@qq.com</email>
</author>
<published>2019-03-25T12:03:49Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=2eb1bef773e099ac93ec74dba7ec216bdf61597c'/>
<id>urn:sha1:2eb1bef773e099ac93ec74dba7ec216bdf61597c</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[libcpu] Add SConscript in libcpu.</title>
<updated>2019-01-06T22:09:45Z</updated>
<author>
<name>Bernard Xiong</name>
<email>bernard.xiong@gmail.com</email>
</author>
<published>2019-01-06T22:09:45Z</published>
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<id>urn:sha1:bde47018b8327fb8106c68e84a719a97243a1653</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[libcpu/arm/cortex-a]rt_hw_interrupt_install函数name参数增加const限定</title>
<updated>2018-12-05T12:35:34Z</updated>
<author>
<name>liruncong</name>
<email>liruncong2018@qq.com</email>
</author>
<published>2018-12-05T12:35:34Z</published>
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<id>urn:sha1:cbe07afabe33e72b9868445c3b2f35d6a2e336e7</id>
<content type='text'>
</content>
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