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<title>rt-thread.git/libcpu/arm/cortex-m0/context_gcc.S, branch v5.2.1</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/rt-thread.git/atom/libcpu/arm/cortex-m0/context_gcc.S?h=v5.2.1</id>
<link rel='self' href='http://cgit.235523.xyz/rt-thread.git/atom/libcpu/arm/cortex-m0/context_gcc.S?h=v5.2.1'/>
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<updated>2022-05-13T07:38:17Z</updated>
<entry>
<title>[libcpu/arm]: fix typo</title>
<updated>2022-05-13T07:38:17Z</updated>
<author>
<name>FrankTan</name>
<email>tfx2001@outlook.com</email>
</author>
<published>2022-05-12T16:18:13Z</published>
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<id>urn:sha1:d2909eb16ba9b3639320dc00f33506a9d228b600</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[libcpu/arm]: add dsb and isb instructions in the end of rt_hw_context_switch_to (#5748)</title>
<updated>2022-04-08T04:52:22Z</updated>
<author>
<name>blta</name>
<email>blta@users.noreply.github.com</email>
</author>
<published>2022-04-08T04:52:22Z</published>
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<id>urn:sha1:b1a9c4c4ea1b02d04f128e9d320dc4f259631d7e</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[asm] 解决tab和空格混用的问题</title>
<updated>2022-01-20T12:57:35Z</updated>
<author>
<name>Meco Man</name>
<email>920369182@qq.com</email>
</author>
<published>2022-01-18T05:35:13Z</published>
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<id>urn:sha1:563e49890c597c53adba954063c37b03644c5c69</id>
<content type='text'>
</content>
</entry>
<entry>
<title>set Systick interrupt priority to the lowest</title>
<updated>2020-05-30T07:23:25Z</updated>
<author>
<name>aozima</name>
<email>wuyangyong@gmail.com</email>
</author>
<published>2020-05-30T07:23:25Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=c3d63e49decf74896fbf3696f181c601ee32f6f0'/>
<id>urn:sha1:c3d63e49decf74896fbf3696f181c601ee32f6f0</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[license] Change the license of libarm to Apache.</title>
<updated>2018-10-14T17:35:07Z</updated>
<author>
<name>Bernard Xiong</name>
<email>bernard.xiong@gmail.com</email>
</author>
<published>2018-10-14T17:35:07Z</published>
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<id>urn:sha1:7c425408b4335d7af2fefcfa51174735b98037ed</id>
<content type='text'>
</content>
</entry>
<entry>
<title>update libcpu: cortex-m0 fault handlers always enable.</title>
<updated>2017-09-01T02:22:55Z</updated>
<author>
<name>aozima</name>
<email>wuyangyong@gmail.com</email>
</author>
<published>2017-09-01T02:22:55Z</published>
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<id>urn:sha1:cb247e913f1b21967b89a0e9724c5f1325e598c4</id>
<content type='text'>
</content>
</entry>
<entry>
<title>update libcpu: ensure fault enable.</title>
<updated>2017-08-18T03:12:58Z</updated>
<author>
<name>aozima</name>
<email>wuyangyong@gmail.com</email>
</author>
<published>2017-08-09T01:49:05Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=9b7303e511b8196d9ba6b8aa292489ead7c51240'/>
<id>urn:sha1:9b7303e511b8196d9ba6b8aa292489ead7c51240</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Fix some spell error;</title>
<updated>2014-07-31T05:59:25Z</updated>
<author>
<name>aozima</name>
<email>wuyangyong@gmail.com</email>
</author>
<published>2014-07-31T05:53:57Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=2c47f2e6838c713a9b64f0e9566b1ca24ad0a9b5'/>
<id>urn:sha1:2c47f2e6838c713a9b64f0e9566b1ca24ad0a9b5</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Fix hardfault bug for gcc port</title>
<updated>2013-11-04T08:10:11Z</updated>
<author>
<name>Bright Pan</name>
<email>loststriker@gmail.com</email>
</author>
<published>2013-11-04T08:10:11Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=06987e72e5e8669fb50ba826344f67d6c6957b15'/>
<id>urn:sha1:06987e72e5e8669fb50ba826344f67d6c6957b15</id>
<content type='text'>
for 2013-02-20 aozima commmit "port for gcc", but the commit is
not tested,and the kernel is breakdown in context_gcc.S, the file
is a copy from cortex-m3,but not port for cortex-m0, so i complete
this port for aozima, test it in stm32f0discovery board ,
and it works fine.
</content>
</entry>
<entry>
<title>fixed bug: correct cortex-m SCB-&gt;VTOR address.</title>
<updated>2013-06-23T10:08:16Z</updated>
<author>
<name>aozima</name>
<email>wuyangyong@gmail.com</email>
</author>
<published>2013-06-23T10:08:16Z</published>
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<id>urn:sha1:b045f93b47d4da57df034e201fff168219880605</id>
<content type='text'>
</content>
</entry>
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