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<title>rt-thread.git/libcpu/arm/cortex-m33/context_gcc.S, branch master</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/rt-thread.git/atom/libcpu/arm/cortex-m33/context_gcc.S?h=master</id>
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<updated>2026-05-19T08:34:34Z</updated>
<entry>
<title>[libcpu][arm][cortex-m33] allows rewrite to interrupt enable/disable api to support independent interrupts management</title>
<updated>2026-05-19T08:34:34Z</updated>
<author>
<name>Evlers</name>
<email>1425295900@qq.com</email>
</author>
<published>2026-05-19T07:07:23Z</published>
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<id>urn:sha1:ad205d2bf36f009a723288638f22fd162e6f327f</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[libcpu/arm/cortex-m33]: Fix incorrect CPU architecture in GCC context switch</title>
<updated>2025-11-02T08:23:31Z</updated>
<author>
<name>Yucai Liu</name>
<email>yucai.liu@sunseekerpower.cn</email>
</author>
<published>2025-11-01T07:21:09Z</published>
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<id>urn:sha1:c91a7f46f576ea89271a29365b36fd3fd0265a01</id>
<content type='text'>
The context_gcc.S file was incorrectly marked as cortex-m4 in both the
doxygen comment and .cpu directive, while the IAR and KEIL versions
correctly specify cortex-m33. This file uses ARMv8-M specific features
(PSPLIM register, TrustZone support) that are not available in Cortex-M4.

Changes:
- Update doxygen group from cortex-m4 to cortex-m33
- Change .cpu directive from cortex-m4 to cortex-m33
</content>
</entry>
<entry>
<title>[libcpu][cortex-m33]Added HardFault_Handler to save floating point registers</title>
<updated>2025-08-20T10:17:19Z</updated>
<author>
<name>Rbb666</name>
<email>zhangbingru@rt-thread.com</email>
</author>
<published>2025-08-20T10:13:15Z</published>
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<id>urn:sha1:882d1958dd45d3a706db8279c5ba0f9be18baf6a</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[libcpu] discard rt_current_thread (#8976)</title>
<updated>2024-05-26T14:00:17Z</updated>
<author>
<name>Shell</name>
<email>smokewood@qq.com</email>
</author>
<published>2024-05-26T14:00:17Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=397cdcd1320d096d41523cbbe0bf743e872d5e70'/>
<id>urn:sha1:397cdcd1320d096d41523cbbe0bf743e872d5e70</id>
<content type='text'>
* [libcpu] rv64: discard rt_current_thread

* arm: using rt_thread_self to fetch current TCB</content>
</entry>
<entry>
<title>实现MPU抽象层 (#8080)</title>
<updated>2023-10-30T12:24:55Z</updated>
<author>
<name>tangzz98</name>
<email>54998890+tangzz98@users.noreply.github.com</email>
</author>
<published>2023-10-30T12:24:55Z</published>
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<id>urn:sha1:acc66c547999ce444b79efccd67625a1af347d5d</id>
<content type='text'>
- 为RT-Thread设计MPU抽象层，支持ARMV7-M，ARMV8-M架构，让用户使用MPU检测栈溢出等内存问题，实现线程内存隔离
- 在components/mp目录下提供通用的API，libcpu目录下提供各处理器架构的具体实现
- 在STM32U575 NUCLEO， STM32H75 NUCLEO开发板测试通过</content>
</entry>
<entry>
<title>[libcpu/arm]: add dsb and isb instructions in the end of rt_hw_context_switch_to (#5748)</title>
<updated>2022-04-08T04:52:22Z</updated>
<author>
<name>blta</name>
<email>blta@users.noreply.github.com</email>
</author>
<published>2022-04-08T04:52:22Z</published>
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<id>urn:sha1:b1a9c4c4ea1b02d04f128e9d320dc4f259631d7e</id>
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</content>
</entry>
<entry>
<title>[bugfix] libcpu/arm/cortex-m/context_gcc: 修复thumb指令集汇编语法错误</title>
<updated>2021-12-09T03:22:46Z</updated>
<author>
<name>jiladahe1997</name>
<email>972931182@qq.com</email>
</author>
<published>2021-12-09T03:22:46Z</published>
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<id>urn:sha1:433e5f81473f71e36fbfb2a4ca5fcbb6b28f57b2</id>
<content type='text'>
当使用thumb指令集时，要求汇编语法中的“条件执行”要跟在IT指令后面，否则会编译不通过。
报错如下：Error: thumb conditional instruction should be in IT block -- `moveq r4,#0x01'

虽然可以通过指定"-Wa,-mimplicit-it=thumb"选项来告诉编译器识别隐式的IT指令，但是能在代码里面直接加上IT指令的话更好。

thumb指令集“条件执行”arm官网文档：
    https://developer.arm.com/documentation/dui0473/m/condition-codes/conditional-execution-in-thumb-state

参考论坛帖子：
    https://club.rt-thread.org/ask/question/433887.html
    https://club.rt-thread.org/ask/question/4188.html

Signed-off-by: Mingrui Ren &lt;jiladahe1997@gmail.com&gt;
</content>
</entry>
<entry>
<title>set Systick interrupt priority to the lowest</title>
<updated>2020-05-30T07:23:25Z</updated>
<author>
<name>aozima</name>
<email>wuyangyong@gmail.com</email>
</author>
<published>2020-05-30T07:23:25Z</published>
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<id>urn:sha1:c3d63e49decf74896fbf3696f181c601ee32f6f0</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[libcpu]context-m33:fix label error in context_gcc.S.</title>
<updated>2020-02-11T13:39:35Z</updated>
<author>
<name>nongxiaoming</name>
<email>nongxiaoming@qq.com</email>
</author>
<published>2020-02-11T13:39:35Z</published>
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<id>urn:sha1:607ed935134baba572671d79561f3ae3624610b2</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[libcpu][cm33] support cortex-m33</title>
<updated>2019-10-29T01:45:17Z</updated>
<author>
<name>tangyuxin</name>
<email>462747508@qq.com</email>
</author>
<published>2019-10-29T01:45:17Z</published>
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<id>urn:sha1:a16f27d84e098934c22faba621322943ee8a061f</id>
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</content>
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