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<title>rt-thread.git/libcpu/arm/cortex-r4, branch v3.0.2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/rt-thread.git/atom/libcpu/arm/cortex-r4?h=v3.0.2</id>
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<updated>2017-12-21T08:37:38Z</updated>
<entry>
<title>[libcpu]: add 8-byte alignment for arm architecture &amp;&amp; optimize code format</title>
<updated>2017-12-21T08:37:38Z</updated>
<author>
<name>SummerGift</name>
<email>zy_770077@qq.com</email>
</author>
<published>2017-12-21T08:32:35Z</published>
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<id>urn:sha1:fc7a5abc7635a1b37bd9202072f279e9930e5eb5</id>
<content type='text'>
</content>
</entry>
<entry>
<title>cortex-r4: use byte to allocate the stack</title>
<updated>2013-11-17T04:49:08Z</updated>
<author>
<name>Grissiom</name>
<email>chaos.proton@gmail.com</email>
</author>
<published>2013-11-17T04:19:04Z</published>
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<id>urn:sha1:0c9b9ced315210159974dcba7d0dc40c18c46ad2</id>
<content type='text'>
Unit of "byte" is more intuitive than "long".
</content>
</entry>
<entry>
<title>cortex-r4: let svc mode reuse the stack of IRQ on startup</title>
<updated>2013-11-17T04:49:07Z</updated>
<author>
<name>Grissiom</name>
<email>chaos.proton@gmail.com</email>
</author>
<published>2013-11-17T04:13:25Z</published>
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<id>urn:sha1:a8520ed383e9557993d647f477ecb4d6658c3ccd</id>
<content type='text'>
As the svc stack is the stack of threads, there is no need to allocate a
separate stack for the startup. Reuse the IRQ stack should be OK.

Tested on rm48 board.
</content>
</entry>
<entry>
<title>cortex-r4: dump register on traps</title>
<updated>2013-10-20T15:46:50Z</updated>
<author>
<name>Grissiom</name>
<email>chaos.proton@gmail.com</email>
</author>
<published>2013-10-20T15:00:44Z</published>
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<id>urn:sha1:377c6e6cc9b415793d4787c86d0e9dea5e47e914</id>
<content type='text'>
We could not handle any traps except IRQ/FIQ.
</content>
</entry>
<entry>
<title>cortex-r4: remove RM48x50.h and add armv7.h</title>
<updated>2013-10-20T13:10:26Z</updated>
<author>
<name>Grissiom</name>
<email>chaos.proton@gmail.com</email>
</author>
<published>2013-10-20T13:09:45Z</published>
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<id>urn:sha1:e1e563e85c831e40c43cb7801434700e779dd750</id>
<content type='text'>
</content>
</entry>
<entry>
<title>rm48: move some asm file to libcpu</title>
<updated>2013-10-20T10:51:46Z</updated>
<author>
<name>Grissiom</name>
<email>chaos.proton@gmail.com</email>
</author>
<published>2013-10-20T10:27:06Z</published>
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<id>urn:sha1:81ab083ae52ee3d1be3804ffe11685802e881bfe</id>
<content type='text'>
</content>
</entry>
<entry>
<title>rm48x50: add GCC support</title>
<updated>2013-10-20T10:51:45Z</updated>
<author>
<name>Grissiom</name>
<email>chaos.proton@gmail.com</email>
</author>
<published>2013-10-19T20:06:56Z</published>
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<id>urn:sha1:9568669109ffcb3aa6de8d07959795de71d505ae</id>
<content type='text'>
</content>
</entry>
<entry>
<title>rm48x50: rt_interrupt_nest should be `volatile rt_uint8_t`</title>
<updated>2013-06-12T15:56:10Z</updated>
<author>
<name>Grissiom</name>
<email>chaos.proton@gmail.com</email>
</author>
<published>2013-06-12T15:56:10Z</published>
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<id>urn:sha1:009239ceeddcdbd4ce5ad573784143df1f485ee8</id>
<content type='text'>
</content>
</entry>
<entry>
<title>rm48x50: add cache_{enable, disable}</title>
<updated>2013-06-12T13:03:04Z</updated>
<author>
<name>Grissiom</name>
<email>chaos.proton@gmail.com</email>
</author>
<published>2013-06-06T07:14:34Z</published>
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<id>urn:sha1:9b949c28b7267ab46cb43abb427309770e64bf84</id>
<content type='text'>
</content>
</entry>
<entry>
<title>cortex-r4: wrap asm functions with .asmfunc/.endasmfunc</title>
<updated>2013-06-05T15:21:06Z</updated>
<author>
<name>Grissiom</name>
<email>chaos.proton@gmail.com</email>
</author>
<published>2013-05-31T14:43:53Z</published>
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<id>urn:sha1:e8bbbe67886f28db5600e6e5029cd24a48925e50</id>
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</entry>
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