rt-thread.git/libcpu/arm/s3c24x0, branch v3.1.5 Unnamed repository; edit this file 'description' to name the repository. http://cgit.235523.xyz/rt-thread.git/atom/libcpu/arm/s3c24x0?h=v3.1.5 2021-05-27T09:33:03Z [lts 3,1,x] format codes 2021-05-27T09:33:03Z Meco Man 920369182@qq.com 2021-05-27T09:33:03Z urn:sha1:03f4d40e30f3c94e1db0b3a65b3610dee695694a [Update] Sync from v4.0.3 2021-02-26T10:23:52Z chenjh chenjinhui@rt-thread.com 2021-02-26T10:23:52Z urn:sha1:055c3d3e1d75fedac44ffb41943350d9844f5b7e Sync from master (0889bafda8e03c6809d43ec87ee28b940efb28aa). 2019-01-19T10:09:18Z armink armink.ztl@gmail.com 2019-01-19T10:09:18Z urn:sha1:0e977c00c4d0ad4a2b8b34491eb1c63f37187a25 [libcpu] Sync to latest version. 2018-12-28T11:22:33Z armink armink.ztl@gmail.com 2018-12-28T11:22:33Z urn:sha1:1bc7b8e61b6967b9443cbe85433af82fd340692e [license] Change the license of libarm to Apache. 2018-10-14T17:35:07Z Bernard Xiong bernard.xiong@gmail.com 2018-10-14T17:35:07Z urn:sha1:7c425408b4335d7af2fefcfa51174735b98037ed [libcpu]: add 8-byte alignment for arm architecture && optimize code format 2017-12-21T08:37:38Z SummerGift zy_770077@qq.com 2017-12-21T08:32:35Z urn:sha1:fc7a5abc7635a1b37bd9202072f279e9930e5eb5 [libcpu] add volatile for __asm. 2017-11-22T01:54:36Z SummerGift zy_770077@qq.com 2017-11-21T09:18:33Z urn:sha1:eb72d191791c72080bc82e1e274c452265e03c5b [libcpu] add volatile for asm (" mcr ") or asm (" mrc ") instruct. 2017-11-22T01:54:27Z SummerGift zy_770077@qq.com 2017-11-21T09:08:49Z urn:sha1:2488624a184fced9df5b2c03c55e1f6db683512e [BSP] change the type of cmd. 2017-10-16T05:23:03Z bernard bernard.xiong@rt-thread.com 2017-10-16T05:23:03Z urn:sha1:5e3b3b19a6994c7113bfa823342b35fbb61287ce 1. Change the type of cmd to 'int'; 2. Remove RT_LWIP_USING_RT_MEM macro; Signed-off-by: visitor83 <wolflouiswang@gmail.com> 2013-06-18T04:51:55Z visitor83 wolflouiswang@gmail.com 2013-06-18T04:51:55Z urn:sha1:c986754c49bd43ef6030b3f5b1215c904fc1d855 format the s3c24x0 serial.c and mini2440 rtconfig.py