rt-thread.git/libcpu/arm, branch copilot/fix-riscv-none-job-failure

[libcpu] Fix RZ/N2L interrupt dispatch

2026-09-10T02:09:17Z

fix[arm][cortex-m4]: clarify MPU permission expressions

2026-09-01T01:39:10Z

[arm][cortex-m4] Add hardware stack guard support

2026-08-26T02:37:02Z

Enable RT_USING_HW_STACK_GUARD on Cortex-M4, which was previously only available on Cortex-M7 and Cortex-M33. Core porting (libcpu/arm/cortex-m4/): - Add mpu.c/mpu.h/mputype.h aligned with the Cortex-M7 MPU layer. The only difference is the default memory type attribute: Cortex-M4 has no L1 cache, so the cacheability bits are reduced to three cases. - Add rt_hw_stack_guard_init() to cpuport.c. - Add missing #include to context_gcc.S and invoke rt_hw_mpu_table_switch() in the PendSV context switch path. - Update SConscript to exclude mpu.c when memory protection is disabled. BSP reference (bsp/stm32/stm32f407-fk407m2-zgt6/): - board.h: include rtthread.h and define NUM_STATIC_REGIONS. - board.c: define static_regions[] marking the Flash region read-only, guarded by RT_USING_MEM_PROTECTION so it is not enabled by default.

refactor(pic): dispatch NVIC IRQs through traps

2026-08-12T04:54:50Z

fix(dm): route Cortex-M resets through power core

2026-08-12T04:54:50Z

feat(dm): support OFW on Cortex-M targets

2026-08-12T04:54:50Z

Add the ARM NVIC PIC driver, no-MMU I/O mapping, built-in FDT support, and Cortex-M CPU hooks required by the native RT-Thread device model.

fix IAR build error

2026-06-02T10:05:02Z

[libcpu][arm][cortex-m33] allows rewrite to interrupt enable/disable api to support independent interrupts management

2026-05-19T08:34:34Z

feat(core): Add Cortex-M4 interrupt context helpers

2026-04-08T10:58:33Z

fix(libcpu): correct arm mpu region validation precedence

2026-04-07T02:13:33Z