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<title>rt-thread.git/libcpu/arm, branch v5.0.x</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/rt-thread.git/atom/libcpu/arm?h=v5.0.x</id>
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<updated>2023-03-31T02:06:28Z</updated>
<entry>
<title>[libcpu/arm/cortex-a] Revert safety MMU initialization. (#6796)</title>
<updated>2023-03-31T02:06:28Z</updated>
<author>
<name>Wayne</name>
<email>wosayttn@gmail.com</email>
</author>
<published>2023-03-31T02:06:28Z</published>
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<id>urn:sha1:3309ef60011f2ddaf8ab32f5c0243c054188f152</id>
<content type='text'>
* Revert safety MMU initialization.

Co-authored-by: Wayne Lin &lt;wclin@nuvoton.com&gt;</content>
</entry>
<entry>
<title>[utest][atomic]添加返回值测试 (#7124)</title>
<updated>2023-03-30T03:06:21Z</updated>
<author>
<name>Yaochenger</name>
<email>75192526+Yaochenger@users.noreply.github.com</email>
</author>
<published>2023-03-30T03:06:21Z</published>
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<id>urn:sha1:38eb3fc40f817ea1dce5223a9bac0d2d3b578bd2</id>
<content type='text'>
* [utest][atomic]添加返回值测试
</content>
</entry>
<entry>
<title>[rt-smart] testcase &amp; improvements for memory management (#7099)</title>
<updated>2023-03-30T00:25:15Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-03-30T00:25:15Z</published>
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<id>urn:sha1:eec78d9f5d3f0a944500a1cac5802dfee2befc7b</id>
<content type='text'>
* [utest/mm] add testcase for create/init
format codes of create/init in components/mm

* [libcpu/aarch64] fix user stack check routine

* [kservice] export API for utest

* [utest/mm] testcase for aspace_map
format &amp; modify the files under components/mm related with aspace_map

* [lwp/user_mm] add user_map_varea for mmap feature

* [mm] rename rt_mm_fault_try_fix to rt_aspace_fault_try_fix

* [utest/mm] testcase for synchronization

* [mm] modify unmap api to improve throughput

* [utest/mm] testcases for cache and varea map

* [format] remove extra space

* [utest/mm] fix testcase problem in header

* [lwp] extend map_user_varea with a flag

* [utest/mm] testcase for lwp_map_user_varea

* [libcpu/arm/cortex-a] fix kernel space layout

* [utest/mm] adjust for armv7 arch</content>
</entry>
<entry>
<title>[atomic]添加arm与risc-v下的常用原子操作函数 (#7053)</title>
<updated>2023-03-23T12:06:50Z</updated>
<author>
<name>Yaochenger</name>
<email>75192526+Yaochenger@users.noreply.github.com</email>
</author>
<published>2023-03-23T12:06:50Z</published>
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<id>urn:sha1:de4f23748212dbba7d0250fdac3ae583e74fcbed</id>
<content type='text'>
* Update Kconfig
* Update trap_gcc.S
* Update bsp/hifive1/drivers/SConscript

Co-authored-by: Man, Jianting (Meco) &lt;920369182@qq.com&gt;
* Update SConscript
* [atomic]提交一份arm与risc-v架构下的常用原子操作函数
* 修改变量类型
* 更新rtatomic.h与atomic_port.c
* 更新rt-thread\libcpu\arm\common\atomic_port.c
* 更新include/rtatomic.h与libcpu/arm/common/SConscript
* 更新include/rtatomic.h
* 修正格式与Kconfig
* 修正格式与文件结构

* 规范文件格式与文件重命名
* 添加测试用例与CI
* 添加函数声明
* 修改virt64/SConscript 添加atomic_riscv.c
  * 1.规范代码风格
  * 2.添加RISC-V64原子指令支持 解决在RV64下编译器将32-bit运算结果扩展为64-bit 导致判断错误
* 添加C11标准库原子操作测试

---------

Co-authored-by: Man, Jianting (Meco) &lt;920369182@qq.com&gt;</content>
</entry>
<entry>
<title>[rt-smart] move sys_cacheflush to lwp_syscall.c (#7048)</title>
<updated>2023-03-17T07:11:38Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-03-17T07:11:38Z</published>
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<id>urn:sha1:18a14cc9351e9c44df539ad21ce825679bc023ca</id>
<content type='text'>
* [syscall] move sys_cacheflush to lwp_syscall.c

* [syscall] improve assertion

* [format] rename to rt_ctassert

* [debug] modified ct assertion on mm_page.c</content>
</entry>
<entry>
<title>[fixup] add cache maintenance ops;</title>
<updated>2023-02-21T00:48:49Z</updated>
<author>
<name>wangxiaoyao</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-02-20T05:48:00Z</published>
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<id>urn:sha1:484a0d602e8b571a9d8186d38c8b136abc4ccfc9</id>
<content type='text'>
fix bugs on cache maintenance when starting user app
</content>
</entry>
<entry>
<title>[rt-smart] PV_OFFSET as a variable (#6904)</title>
<updated>2023-02-14T15:08:32Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-02-14T15:08:32Z</published>
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<id>urn:sha1:2d0974908659bd41d748e69fac0166c37b15cb02</id>
<content type='text'>
* [rt-smart/mem] remove pv_offset

* [rt-smart] list kernel space command

* [rt-smart] restore ioremap region

* [revert] restore kernel space isolation

* [rt-smart/pv_off] code format

* [rt-smart] add get_pvoff()

* [pvoffset] pvoff as constant for C codes

* [pvoff] pvoff as interfaces</content>
</entry>
<entry>
<title>rt_device_write/read return data type as rt_ssize_t</title>
<updated>2023-02-08T02:43:57Z</updated>
<author>
<name>Meco Man</name>
<email>920369182@qq.com</email>
</author>
<published>2023-02-05T23:35:33Z</published>
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<id>urn:sha1:f58d3c5200d5a51a39503c5311422e2fb99d3d20</id>
<content type='text'>
rt_ssize_t can give negative error code, which follows the unix style correctly
</content>
</entry>
<entry>
<title>[cortex-m7]rt_hw_cpu_dcache_ops函数uint32_t替换为rt_uint32_t</title>
<updated>2023-02-07T17:05:27Z</updated>
<author>
<name>wdfk-prog</name>
<email>1425075683@qq.com</email>
</author>
<published>2023-02-07T12:14:35Z</published>
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<id>urn:sha1:72961172033fcb3a96e6fb1758b5ca0e1aebe455</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[rt-smart] kernel virtual memory management layer (#6809)</title>
<updated>2023-01-09T02:08:55Z</updated>
<author>
<name>Shell</name>
<email>wangxiaoyao@rt-thread.com</email>
</author>
<published>2023-01-09T02:08:55Z</published>
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<id>urn:sha1:7450ef6c4d71f992444d27f4a26c16f813ed8e55</id>
<content type='text'>
synchronize virtual memory system works.
adding kernel virtual memory management layer for page-based MMU enabled architecture
porting libcpu MMU codes
porting lwp memory related codes</content>
</entry>
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