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<title>rt-thread.git/libcpu/arm, branch v5.3.0</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
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<updated>2026-09-10T09:54:43Z</updated>
<entry>
<title>[libcpu] Fix RZ/N2L interrupt dispatch</title>
<updated>2026-09-10T09:54:43Z</updated>
<author>
<name>CYFS</name>
<email>2805686936@qq.com</email>
</author>
<published>2026-08-28T09:50:18Z</published>
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(cherry picked from commit fe966755e9d9b207b9271afd38e5086624328af4)
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</entry>
<entry>
<title>refactor(pic): dispatch NVIC IRQs through traps</title>
<updated>2026-08-12T04:54:50Z</updated>
<author>
<name>Rbb666</name>
<email>zhangbingru@rt-thread.com</email>
</author>
<published>2026-08-03T03:54:48Z</published>
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<id>urn:sha1:46fdeefb3239f8f4a22a373fc6fd362499389c9e</id>
<content type='text'>
</content>
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<entry>
<title>fix(dm): route Cortex-M resets through power core</title>
<updated>2026-08-12T04:54:50Z</updated>
<author>
<name>Rbb666</name>
<email>zhangbingru@rt-thread.com</email>
</author>
<published>2026-08-03T03:54:06Z</published>
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<id>urn:sha1:1f23e3f27052a6b7fd75def2da634c79db5773e2</id>
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<entry>
<title>feat(dm): support OFW on Cortex-M targets</title>
<updated>2026-08-12T04:54:50Z</updated>
<author>
<name>Rbb666</name>
<email>zhangbingru@rt-thread.com</email>
</author>
<published>2026-07-31T07:07:36Z</published>
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<id>urn:sha1:6b4f34204ed2da80b7c37b912612c65cebc30ce3</id>
<content type='text'>
Add the ARM NVIC PIC driver, no-MMU I/O mapping, built-in FDT support, and Cortex-M CPU hooks required by the native RT-Thread device model.
</content>
</entry>
<entry>
<title>fix IAR build error</title>
<updated>2026-06-02T10:05:02Z</updated>
<author>
<name>蒙蒙plus</name>
<email>chengmeng_2@outlook.com</email>
</author>
<published>2026-05-28T10:08:24Z</published>
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<entry>
<title>[libcpu][arm][cortex-m33] allows rewrite to interrupt enable/disable api to support independent interrupts management</title>
<updated>2026-05-19T08:34:34Z</updated>
<author>
<name>Evlers</name>
<email>1425295900@qq.com</email>
</author>
<published>2026-05-19T07:07:23Z</published>
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<id>urn:sha1:ad205d2bf36f009a723288638f22fd162e6f327f</id>
<content type='text'>
</content>
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<entry>
<title>feat(core): Add Cortex-M4 interrupt context helpers</title>
<updated>2026-04-08T10:58:33Z</updated>
<author>
<name>wdfk-prog</name>
<email>1425075683@qq.com</email>
</author>
<published>2026-04-08T05:45:46Z</published>
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<id>urn:sha1:e74547bbb36c38bbebf8baca4d728b3db14885df</id>
<content type='text'>
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<entry>
<title>fix(libcpu): correct arm mpu region validation precedence</title>
<updated>2026-04-07T02:13:33Z</updated>
<author>
<name>AFWEF_147</name>
<email>olm_cse@hust.edu.cn</email>
</author>
<published>2026-03-26T13:55:23Z</published>
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<id>urn:sha1:2960935d2e34623a316fd0e9c5f6399d9e937f04</id>
<content type='text'>
</content>
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<entry>
<title>fix(libcpu): validate arm irq vectors before masking</title>
<updated>2026-04-07T02:07:41Z</updated>
<author>
<name>AFWEF_147</name>
<email>olm_cse@hust.edu.cn</email>
</author>
<published>2026-03-26T13:55:23Z</published>
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<id>urn:sha1:21d223f08986e3252eb0e8ff4510efe0e0e3877c</id>
<content type='text'>
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<entry>
<title>[docs][libcpu][arm][cortex-a] correct TLBIALL comments in start_gcc.S</title>
<updated>2026-04-03T12:13:35Z</updated>
<author>
<name>laidene</name>
<email>228526434@qq.com</email>
</author>
<published>2026-04-02T01:36:07Z</published>
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