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<title>rt-thread.git/libcpu/mips/common/exception.c, branch v5.1.0</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
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<updated>2023-04-14T06:06:43Z</updated>
<entry>
<title>[HUST][CSE]mips/common/exception.c/rt_set_except_vector (#7238)</title>
<updated>2023-04-14T06:06:43Z</updated>
<author>
<name>d1zzy126</name>
<email>u202112512@hust.edu.cn</email>
</author>
<published>2023-04-14T06:06:43Z</published>
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<id>urn:sha1:5c1b071a0ce8ad5a120ec32e37ffc9c17fb09b29</id>
<content type='text'>
* mips/common/exception.c/rt_set_except_vector

* Update exception.c

---------

Co-authored-by: Bernard Xiong &lt;bernard.xiong@gmail.com&gt;</content>
</entry>
<entry>
<title>uniform code writing-disable interrupt</title>
<updated>2022-04-20T06:22:43Z</updated>
<author>
<name>thewon86</name>
<email>zhongyong0104@sina.com</email>
</author>
<published>2022-04-20T02:56:11Z</published>
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<id>urn:sha1:f5b0bfd3f4f450424b5bc1f084959d0436c8a6e6</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[libcpu] auto formatted</title>
<updated>2021-03-27T09:51:56Z</updated>
<author>
<name>Meco Man</name>
<email>920369182@qq.com</email>
</author>
<published>2021-03-27T09:51:56Z</published>
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<id>urn:sha1:6c907c3a477b1f34ca1adb277748c3306110cabf</id>
<content type='text'>
</content>
</entry>
<entry>
<title>MIPS:fix the RT_EXCEPTION_MAX value</title>
<updated>2020-09-14T03:10:44Z</updated>
<author>
<name>michael</name>
<email>michael5hzg@gmail.com</email>
</author>
<published>2020-09-14T03:10:44Z</published>
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<id>urn:sha1:a8928c881ed935a1e2a45bb02bd0b2a7fe8d45d4</id>
<content type='text'>
from &lt;see mips run&gt; know that cp0_cause's ExcCode have 5 bit filed and
the max exception is 32.
</content>
</entry>
<entry>
<title>fixed loongson bsp build on windows</title>
<updated>2020-09-04T03:57:35Z</updated>
<author>
<name>bigmagic</name>
<email>zhaofujin@rt-thread.com</email>
</author>
<published>2020-09-04T03:57:35Z</published>
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<id>urn:sha1:c66314a8b6a12412e34440e8369d9c77d43aaada</id>
<content type='text'>
</content>
</entry>
<entry>
<title>add ls2k mmu</title>
<updated>2020-09-04T02:16:34Z</updated>
<author>
<name>bigmagic</name>
<email>zhaofujin@rt-thread.com</email>
</author>
<published>2020-09-04T01:31:42Z</published>
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<id>urn:sha1:1556ba8e7f84f34c56c7f3c13d5a5540371658d4</id>
<content type='text'>
</content>
</entry>
<entry>
<title>fix ls2k libc and irq</title>
<updated>2020-06-21T15:28:11Z</updated>
<author>
<name>bigamgic</name>
<email>zhaofujin@rt-thread.com</email>
</author>
<published>2020-06-21T15:25:32Z</published>
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<id>urn:sha1:1ec681a55121b9b1d5fcdb274a3c3d10d408a960</id>
<content type='text'>
</content>
</entry>
<entry>
<title>add ls2k bsp config</title>
<updated>2020-04-07T06:39:20Z</updated>
<author>
<name>bigmagic</name>
<email>zhaofujin@rt-thread.com</email>
</author>
<published>2020-04-07T03:26:30Z</published>
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<id>urn:sha1:c024e2e485c813aa1c70e079f61fe50a80d8215c</id>
<content type='text'>
</content>
</entry>
<entry>
<title>fix mips64 some bug</title>
<updated>2020-04-07T06:39:12Z</updated>
<author>
<name>bigmagic</name>
<email>zhaofujin@rt-thread.com</email>
</author>
<published>2020-04-06T07:46:28Z</published>
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<id>urn:sha1:990f731b776055390db854f9cc980799e39247e8</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[libcpu] Refine MIPS common code</title>
<updated>2019-12-11T07:24:04Z</updated>
<author>
<name>Jiaxun Yang</name>
<email>jiaxun.yang@flygoat.com</email>
</author>
<published>2019-12-06T16:54:03Z</published>
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<id>urn:sha1:7c6650186100add61ef16c13fb120ad1161f6f1d</id>
<content type='text'>
MIPS common code was highly duplicated, This commit
is a attempt to clean-up and refine these code.

The context and exception handle flow is mostly identical
with Linux, but a notable difference is that when FPU enabled,
we save FP registers in stackframe unconditionally.

Signed-off-by: Jiaxun Yang &lt;jiaxun.yang@flygoat.com&gt;
</content>
</entry>
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