rt-thread.git/libcpu/mips/gs232/cache.c, branch v5.3.0 Unnamed repository; edit this file 'description' to name the repository. http://cgit.235523.xyz/rt-thread.git/atom/libcpu/mips/gs232/cache.c?h=v5.3.0 2023-04-18T03:45:10Z fix:fixed variable misuse 2023-04-18T03:45:10Z zb1tree m202271786@hust.edu.cn 2023-04-16T08:35:32Z urn:sha1:a25d3fd30133e7ff0087e63b3794bdf6463ca26b [libcpu] auto formatted 2021-03-27T09:51:56Z Meco Man 920369182@qq.com 2021-03-27T09:51:56Z urn:sha1:6c907c3a477b1f34ca1adb277748c3306110cabf [libcpu] mips: Merge loongson_1 into gs232 2019-12-11T07:24:42Z Jiaxun Yang jiaxun.yang@flygoat.com 2019-12-06T16:55:46Z urn:sha1:9ef986929cb2c39485da89ec39ad80316a5a9965 Previously Loongson 1B and Loongson 1C have their own libcpu implemention, but they're almost identical. So we merge them into gs232 and adapt to new common code. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>