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<title>rt-thread.git/libcpu/risc-v/common/SConscript, branch master</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/rt-thread.git/atom/libcpu/risc-v/common/SConscript?h=master</id>
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<updated>2026-10-17T01:44:26Z</updated>
<entry>
<title>[ARCH/RISC-V] Next RISC-V (#10320)</title>
<updated>2026-10-17T01:44:26Z</updated>
<author>
<name>GUI</name>
<email>39894654+GuEe-GUI@users.noreply.github.com</email>
</author>
<published>2026-10-17T01:44:26Z</published>
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<id>urn:sha1:8d8dc96b67eee53af2841a8819364d52fbec39cb</id>
<content type='text'>
* [libcpu][risc-v] Refactor the RISC-V architecture port

Introduce an opt-in unified RISC-V common layer for RV32 and RV64 while keeping existing BSPs on the legacy implementation during migration.

- use ARCH_RISCV and ARCH_CPU_64BIT for architecture and XLEN selection
- unify context, trap, MMU, cache, timer, SBI, SMP and ISA handling
- add PLIC, CLIC, ACLINT, APLIC and IMSIC support
- map physical hart IDs to contiguous logical CPU IDs
- add T-Head vendor overrides while preserving legacy ports
- migrate qemu-virt64-riscv with RV32 and RV64 support
- update clock_time, MM, LWP, OFW, PCI and Rust integration

Existing BSPs continue using legacy_common or common64 unless they select RT_USING_RISCV_NEW_COMMON.

Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;

* [libcpu][risc-v] skip disabled CPU nodes in early FDT walk

Rbb666 noted that rt_hw_fdt_install_early() walked every /cpus child
without checking status, so disabled cores still joined hart registration
and MMU capability probing. Skip nodes that are not okay/ok via
rt_fdt_device_is_available() before reading reg or mmu-type.

Signed-off-by: seteiro &lt;chenmoushun@163.com&gt;

* [libcpu][risc-v] Fix per-CPU page table mapping

- reuse existing non-leaf page table entries when mapping per-CPU areas
- reject leaf entry conflicts instead of overwriting mappings

Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;

---------

Signed-off-by: GuEe-GUI &lt;2991707448@qq.com&gt;
Signed-off-by: seteiro &lt;chenmoushun@163.com&gt;
Co-authored-by: seteiro &lt;chenmoushun@163.com&gt;</content>
</entry>
<entry>
<title>Reorganize Group names in build system for clarity and IDE integration #10923</title>
<updated>2025-11-16T03:40:53Z</updated>
<author>
<name>Copilot</name>
<email>198982749+Copilot@users.noreply.github.com</email>
</author>
<published>2025-11-16T03:40:53Z</published>
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<id>urn:sha1:30e1e5e9dcdaff17258edf70b9f9783e08356288</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[libcpu][SConscript]规范group名为libcpu</title>
<updated>2024-02-20T00:39:05Z</updated>
<author>
<name>Meco Man</name>
<email>920369182@qq.com</email>
</author>
<published>2024-02-19T19:33:47Z</published>
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<id>urn:sha1:6d4503363a352c72148bc91da3026f0db096f119</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[atomic]添加arm与risc-v下的常用原子操作函数 (#7053)</title>
<updated>2023-03-23T12:06:50Z</updated>
<author>
<name>Yaochenger</name>
<email>75192526+Yaochenger@users.noreply.github.com</email>
</author>
<published>2023-03-23T12:06:50Z</published>
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<id>urn:sha1:de4f23748212dbba7d0250fdac3ae583e74fcbed</id>
<content type='text'>
* Update Kconfig
* Update trap_gcc.S
* Update bsp/hifive1/drivers/SConscript

Co-authored-by: Man, Jianting (Meco) &lt;920369182@qq.com&gt;
* Update SConscript
* [atomic]提交一份arm与risc-v架构下的常用原子操作函数
* 修改变量类型
* 更新rtatomic.h与atomic_port.c
* 更新rt-thread\libcpu\arm\common\atomic_port.c
* 更新include/rtatomic.h与libcpu/arm/common/SConscript
* 更新include/rtatomic.h
* 修正格式与Kconfig
* 修正格式与文件结构

* 规范文件格式与文件重命名
* 添加测试用例与CI
* 添加函数声明
* 修改virt64/SConscript 添加atomic_riscv.c
  * 1.规范代码风格
  * 2.添加RISC-V64原子指令支持 解决在RV64下编译器将32-bit运算结果扩展为64-bit 导致判断错误
* 添加C11标准库原子操作测试

---------

Co-authored-by: Man, Jianting (Meco) &lt;920369182@qq.com&gt;</content>
</entry>
<entry>
<title>format Kconfig and sconscript</title>
<updated>2023-01-09T03:52:13Z</updated>
<author>
<name>Meco Man</name>
<email>920369182@qq.com</email>
</author>
<published>2023-01-09T02:14:23Z</published>
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<id>urn:sha1:9bc68d26a446158aad13f910fa5a2b8b09febec1</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[libcpu][riscv]移除cv32e40p中部分文件，采用common中的文件</title>
<updated>2023-01-02T21:42:18Z</updated>
<author>
<name>Yaochenger</name>
<email>1516081466@qq.com</email>
</author>
<published>2022-12-30T06:51:02Z</published>
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<id>urn:sha1:f2a66e122fbd702941d0a3c6fef92af605eb4b6e</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[SConscript]update group name</title>
<updated>2020-12-19T08:49:11Z</updated>
<author>
<name>yangjie</name>
<email>yangjiexaut@126.com</email>
</author>
<published>2020-12-19T08:49:11Z</published>
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<id>urn:sha1:ef62febf1f2461bdd72efcffde050905865a99c5</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[SConscript] change libcpu to LIBARCH,and correcte letter case</title>
<updated>2020-11-30T07:52:43Z</updated>
<author>
<name>yangjie11</name>
<email>yangjiexaut@126.com</email>
</author>
<published>2020-11-30T07:45:58Z</published>
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<id>urn:sha1:ba83ddc3c4e2fc16865b43f87081ab403a4941a9</id>
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</content>
</entry>
<entry>
<title>[SConscript]rename group name</title>
<updated>2020-11-20T05:38:11Z</updated>
<author>
<name>yangjie11</name>
<email>yangjiexaut@126.com</email>
</author>
<published>2020-11-20T05:38:11Z</published>
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<id>urn:sha1:91261e25b90d6258073f620ae14c003dae9eb16e</id>
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</content>
</entry>
<entry>
<title>[libcpu] Add SConscript in libcpu.</title>
<updated>2019-01-06T22:09:45Z</updated>
<author>
<name>Bernard Xiong</name>
<email>bernard.xiong@gmail.com</email>
</author>
<published>2019-01-06T22:09:45Z</published>
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<id>urn:sha1:bde47018b8327fb8106c68e84a719a97243a1653</id>
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</content>
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