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<title>rt-thread.git/libcpu/risc-v/common/cpuport.h, branch serialX-dev</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/rt-thread.git/atom/libcpu/risc-v/common/cpuport.h?h=serialX-dev</id>
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<updated>2023-01-05T02:06:09Z</updated>
<entry>
<title>[libcpu][riscv]移除ch32中的冗余文件,使用common下的文件 (#6813)</title>
<updated>2023-01-05T02:06:09Z</updated>
<author>
<name>Yaochenger</name>
<email>75192526+Yaochenger@users.noreply.github.com</email>
</author>
<published>2023-01-05T02:06:09Z</published>
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<id>urn:sha1:b99769f68635e2644e3ad5082409948c15778372</id>
<content type='text'>
* [libcpu][riscv]移除ch32中的冗余文件,使用common下的文件

* 修正cpuport.h宏定义

* 规范宏定义格式</content>
</entry>
<entry>
<title>sync branch rt-smart. (#6641)</title>
<updated>2022-12-03T04:07:44Z</updated>
<author>
<name>guo</name>
<email>guozhanxin@rt-thread.com</email>
</author>
<published>2022-12-03T04:07:44Z</published>
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<id>urn:sha1:ecf2d8215961ca7c539132b62a72df6072cc3e14</id>
<content type='text'>
* Synchronize the code of the rt mart branch to the master branch.
  * TTY device
  * Add lwP code from rt-smart
  * Add vnode in DFS, but DFS will be re-write for rt-smart
  * There are three libcpu for rt-smart:
    * arm/cortex-a, arm/aarch64
    * riscv64

Co-authored-by: Rbb666 &lt;zhangbingru@rt-thread.com&gt;
Co-authored-by: zhkag &lt;zhkag@foxmail.com&gt;</content>
</entry>
<entry>
<title>[libcpu] auto formatted</title>
<updated>2021-03-27T09:51:56Z</updated>
<author>
<name>Meco Man</name>
<email>920369182@qq.com</email>
</author>
<published>2021-03-27T09:51:56Z</published>
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<id>urn:sha1:6c907c3a477b1f34ca1adb277748c3306110cabf</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[libcpu/risc-v][K210] add FPU support</title>
<updated>2020-11-20T05:53:50Z</updated>
<author>
<name>tangweikang</name>
<email>tangweikang@rt-thread.com</email>
</author>
<published>2020-11-20T04:05:37Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/rt-thread.git/commit/?id=c8deffcf56df79cbf817b02cb1d9b62c61565022'/>
<id>urn:sha1:c8deffcf56df79cbf817b02cb1d9b62c61565022</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[libcpu] Add unified RISC-V libcpu porting.</title>
<updated>2018-12-08T02:41:38Z</updated>
<author>
<name>Bernard Xiong</name>
<email>bernard.xiong@gmail.com</email>
</author>
<published>2018-12-08T02:41:38Z</published>
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<id>urn:sha1:2a7d814f77a42da4dc126a9e75f6e8705f6bf0cd</id>
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