[ARCH/RISC-V] Next RISC-V (#10320)

2026-10-17T01:44:26Z

* [libcpu][risc-v] Refactor the RISC-V architecture port Introduce an opt-in unified RISC-V common layer for RV32 and RV64 while keeping existing BSPs on the legacy implementation during migration. - use ARCH_RISCV and ARCH_CPU_64BIT for architecture and XLEN selection - unify context, trap, MMU, cache, timer, SBI, SMP and ISA handling - add PLIC, CLIC, ACLINT, APLIC and IMSIC support - map physical hart IDs to contiguous logical CPU IDs - add T-Head vendor overrides while preserving legacy ports - migrate qemu-virt64-riscv with RV32 and RV64 support - update clock_time, MM, LWP, OFW, PCI and Rust integration Existing BSPs continue using legacy_common or common64 unless they select RT_USING_RISCV_NEW_COMMON. Signed-off-by: GuEe-GUI <2991707448@qq.com> * [libcpu][risc-v] skip disabled CPU nodes in early FDT walk Rbb666 noted that rt_hw_fdt_install_early() walked every /cpus child without checking status, so disabled cores still joined hart registration and MMU capability probing. Skip nodes that are not okay/ok via rt_fdt_device_is_available() before reading reg or mmu-type. Signed-off-by: seteiro * [libcpu][risc-v] Fix per-CPU page table mapping - reuse existing non-leaf page table entries when mapping per-CPU areas - reject leaf entry conflicts instead of overwriting mappings Signed-off-by: GuEe-GUI <2991707448@qq.com> --------- Signed-off-by: GuEe-GUI <2991707448@qq.com> Signed-off-by: seteiro Co-authored-by: seteiro

bsp: qemu-virt64-riscv: remove config RISCV_S_MODE

2025-01-10T09:14:13Z

RISCV_S_MODE configuration only affects the code in libcpu/risc-v/virt64, and the only bsp using this libcpu is qemu-virt64-riscv. Considering s-mode is the default mode RT-Thread running on virt64 machine, it seems unnecessary to make RISCV_S_MODE a Kconfig option. Solution: Remove RISCV_S_MODE from Kconfig and define it as a macro in the code in libcpu/risc-v/virt64. Plus, due to this macro is only related to virt64, rename RISCV_S_MODE to RISCV_VIRT64_S_MODE. Update the .config/rtconfig.h in this patch. Signed-off-by: Chen Wang

[libcpu][risc-v]add README for RV64

2024-10-08T21:56:55Z

rt-thread.git/libcpu/risc-v/common64/README.md, branch master

[ARCH/RISC-V] Next RISC-V (#10320)

bsp: qemu-virt64-riscv: remove config RISCV_S_MODE

[libcpu][risc-v]add README for RV64