rt-thread.git/libcpu/risc-v/common64/stackframe.h, branch masterUnnamed repository; edit this file 'description' to name the repository.http://cgit.235523.xyz/rt-thread.git/atom/libcpu/risc-v/common64/stackframe.h?h=master2026-10-17T01:44:26Z[ARCH/RISC-V] Next RISC-V (#10320)2026-10-17T01:44:26ZGUI39894654+GuEe-GUI@users.noreply.github.com2026-10-17T01:44:26Zurn:sha1:8d8dc96b67eee53af2841a8819364d52fbec39cb
* [libcpu][risc-v] Refactor the RISC-V architecture port
Introduce an opt-in unified RISC-V common layer for RV32 and RV64 while keeping existing BSPs on the legacy implementation during migration.
- use ARCH_RISCV and ARCH_CPU_64BIT for architecture and XLEN selection
- unify context, trap, MMU, cache, timer, SBI, SMP and ISA handling
- add PLIC, CLIC, ACLINT, APLIC and IMSIC support
- map physical hart IDs to contiguous logical CPU IDs
- add T-Head vendor overrides while preserving legacy ports
- migrate qemu-virt64-riscv with RV32 and RV64 support
- update clock_time, MM, LWP, OFW, PCI and Rust integration
Existing BSPs continue using legacy_common or common64 unless they select RT_USING_RISCV_NEW_COMMON.
Signed-off-by: GuEe-GUI <2991707448@qq.com>
* [libcpu][risc-v] skip disabled CPU nodes in early FDT walk
Rbb666 noted that rt_hw_fdt_install_early() walked every /cpus child
without checking status, so disabled cores still joined hart registration
and MMU capability probing. Skip nodes that are not okay/ok via
rt_fdt_device_is_available() before reading reg or mmu-type.
Signed-off-by: seteiro <chenmoushun@163.com>
* [libcpu][risc-v] Fix per-CPU page table mapping
- reuse existing non-leaf page table entries when mapping per-CPU areas
- reject leaf entry conflicts instead of overwriting mappings
Signed-off-by: GuEe-GUI <2991707448@qq.com>
---------
Signed-off-by: GuEe-GUI <2991707448@qq.com>
Signed-off-by: seteiro <chenmoushun@163.com>
Co-authored-by: seteiro <chenmoushun@163.com>[lwp][rv64] restore tp register in arch_thread_signal_enter to fix user-mode memory access2025-07-23T01:38:35ZYulong Wang2302147681@qq.com2025-07-12T13:10:48Zurn:sha1:e7a40ae6ec1fdcb0d74a4902cfbd50aee7ee8e8f[libcpu]添加对riscv vector的支持 (#9531)2024-10-16T06:10:09Zheyuanjie87943313837@qq.com2024-10-16T06:10:09Zurn:sha1:49b661476393bd9c9fc199362cf4b008c35a9340
[libcpu]添加对riscv vector的支持feat: remove redundant codes under virt64, c9062024-09-13T21:35:00ZShellsmokewood@qq.com2024-09-12T03:14:12Zurn:sha1:57d002b25e26a5df950b087f0ea2dc7b6feeb7e3
Changes:
- create new folder name `common64` and save all common codes of rv64
inside
Signed-off-by: Shell <smokewood@qq.com>