rt-thread.git/libcpu/risc-v/common64, branch v5.2.0-beta

[libcpu][risc-v]add comments for rv64 sv39 mmu APIs. (#10053)

2025-03-10T14:47:50Z

[bugfix][risc-v]fix the PPN length error in GET_PPN(pte). (#10020)

2025-03-10T14:47:03Z

libcpu: riscv: fixed ARCH_RISCV_VECTOR issue

2025-03-10T14:44:46Z

description: Using the vector instruction set to trigger an illegal instruction exception when ARCH_SISCV_VECTOR=y. analysis: When initializing the thread stack, the rt_cw_stack_init function did not enable VS for SSTATUS. Solution: When ARCH_SISCV_VECTOR=y, increment the initial value of sstatus by 0x600(SSTATUS_VS). Signed-off-by: Liu Gui

bsp: qemu-virt64-riscv: remove config RISCV_S_MODE

2025-01-10T09:14:13Z

RISCV_S_MODE configuration only affects the code in libcpu/risc-v/virt64, and the only bsp using this libcpu is qemu-virt64-riscv. Considering s-mode is the default mode RT-Thread running on virt64 machine, it seems unnecessary to make RISCV_S_MODE a Kconfig option. Solution: Remove RISCV_S_MODE from Kconfig and define it as a macro in the code in libcpu/risc-v/virt64. Plus, due to this macro is only related to virt64, rename RISCV_S_MODE to RISCV_VIRT64_S_MODE. Update the .config/rtconfig.h in this patch. Signed-off-by: Chen Wang

[libcpu/riscv]解决smp下cpuport.h中的编译问题 (#9714)

2024-11-29T01:39:41Z

[libcpu][riscv]纠正pv_offset的对齐检查

2024-11-22T00:23:11Z

[libcpu]riscv使用call指令解决长跳转问题

2024-11-15T06:34:32Z

[libcpu]添加对riscv vector的支持 (#9531)

2024-10-16T06:10:09Z

[libcpu]添加对riscv vector的支持

[libcpu][risc-v] fix the bug when using ASID in the RV64 MMU

2024-10-11T04:10:46Z

* (fix) mmu: satp value should be 64-bit Corrected the SATP register to ensure it uses the correct 64-bit format as required by the system architecture. * use __asm__ instead of asm for the GNU C compiler Co-authored-by: Shell --------- Co-authored-by: Shell

[libcpu][risc-v]remove the redundant "0x" from the printed information when cpu is in exception (#9516)

2024-10-09T07:46:39Z

Remove redundant '0x' from printed output