rt-thread.git/libcpu/risc-v/common, branch master

[libcpu][risc-v] Fix ticket spinlock stalls under SMP contention

2026-10-22T09:59:29Z

Eight-core boot on SpacemiT K1 could stall with one CPU in the unlock LR/SC loop, two CPUs allocating tickets, and the remaining CPUs waiting for the scheduler lock. Replace LR/SC ticket allocation with amoadd.w.aqrl and release the lock with a halfword owner update. Order critical-section accesses after acquiring ownership and before releasing it. Verified eight-core boot on K1 with temporary diagnostics and reservation-clearing changes removed. Signed-off-by: GuEe-GUI <2991707448@qq.com>

[bsp][spacemit/k1] first version #11132

2026-10-19T10:49:16Z

[ARCH/RISC-V] Next RISC-V (#10320)

2026-10-17T01:44:26Z

* [libcpu][risc-v] Refactor the RISC-V architecture port Introduce an opt-in unified RISC-V common layer for RV32 and RV64 while keeping existing BSPs on the legacy implementation during migration. - use ARCH_RISCV and ARCH_CPU_64BIT for architecture and XLEN selection - unify context, trap, MMU, cache, timer, SBI, SMP and ISA handling - add PLIC, CLIC, ACLINT, APLIC and IMSIC support - map physical hart IDs to contiguous logical CPU IDs - add T-Head vendor overrides while preserving legacy ports - migrate qemu-virt64-riscv with RV32 and RV64 support - update clock_time, MM, LWP, OFW, PCI and Rust integration Existing BSPs continue using legacy_common or common64 unless they select RT_USING_RISCV_NEW_COMMON. Signed-off-by: GuEe-GUI <2991707448@qq.com> * [libcpu][risc-v] skip disabled CPU nodes in early FDT walk Rbb666 noted that rt_hw_fdt_install_early() walked every /cpus child without checking status, so disabled cores still joined hart registration and MMU capability probing. Skip nodes that are not okay/ok via rt_fdt_device_is_available() before reading reg or mmu-type. Signed-off-by: seteiro * [libcpu][risc-v] Fix per-CPU page table mapping - reuse existing non-leaf page table entries when mapping per-CPU areas - reject leaf entry conflicts instead of overwriting mappings Signed-off-by: GuEe-GUI <2991707448@qq.com> --------- Signed-off-by: GuEe-GUI <2991707448@qq.com> Signed-off-by: seteiro Co-authored-by: seteiro

[bsp/gd32] fix gd32vw553 bsp

2026-02-25T06:54:20Z

update: [libcpu][risc-v][common] allow overriding isr numbers for MCU

2025-12-11T09:04:14Z

- allow overriding the isr numbers via RT_HW_ISR_NUM macro Signed-off-by: Fan YANG

Reorganize Group names in build system for clarity and IDE integration #10923

2025-11-16T03:40:53Z

移除无用文件，该文件未被任何BSP使用

2025-05-30T01:32:08Z

[libcpu/common] 修正对RV32E的支持，RV32E不支持s2寄存器，修改为s1寄存器

2025-05-30T01:32:08Z

[libcpu][riscv] add a doc for wch saving the irq stack as stack-512 (#10063)

2025-03-03T15:13:11Z

libcpu: riscv: common: fixed build warnings

2025-01-30T01:28:38Z

When building bsp/cvitek/c906_little, compiler warns: ``` .../rt-thread/libcpu/risc-v/common/trap_common.c: In function 'rt_hw_interrupt_install': .../rt-thread/libcpu/risc-v/common/trap_common.c:50:11: warning: unused variable 'user_param' [-Wunused-variable] 50 | void *user_param = param; | ^~~~~~~~~~ .../rt-thread/libcpu/risc-v/common/trap_common.c: In function 'rt_rv32_system_irq_handler': .../rt-thread/libcpu/risc-v/common/trap_common.c:77:25: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] 77 | s_stack_frame = (rt_hw_stack_frame_t *)mscratch; | ^ ``` Fixed these warnings as per indication from gcc. Signed-off-by: Chen Wang