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<title>rt-thread.git/libcpu/risc-v/common, branch v5.0.2</title>
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<id>http://cgit.235523.xyz/rt-thread.git/atom/libcpu/risc-v/common?h=v5.0.2</id>
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<updated>2023-08-12T01:20:28Z</updated>
<entry>
<title>[libcpu][risc-v][common] Fix application crash on risc-v soc if FPU is</title>
<updated>2023-08-12T01:20:28Z</updated>
<author>
<name>Fan YANG</name>
<email>fan.yang@hpmicro.com</email>
</author>
<published>2023-08-11T13:05:52Z</published>
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<id>urn:sha1:5308cc47161d8e2f9fdb680738e023ef16af1e2b</id>
<content type='text'>
enabled

- Defined ARCH_RISCV_FPU once the __riscv_flen macro was detected

Signed-off-by: Fan YANG &lt;fan.yang@hpmicro.com&gt;
</content>
</entry>
<entry>
<title>[libcpu][risc-v][common] Avoid using t0 before being saved</title>
<updated>2023-08-09T05:07:11Z</updated>
<author>
<name>Fan YANG</name>
<email>fan.yang@hpmicro.com</email>
</author>
<published>2023-08-09T02:51:32Z</published>
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<id>urn:sha1:5ac509b6d031b29e2d95c52fc179771e62664378</id>
<content type='text'>
- Fixed the issue that t0 was modified unexpectedly before being saved

Signed-off-by: Fan YANG &lt;fan.yang@hpmicro.com&gt;
</content>
</entry>
<entry>
<title>rt_hw_cpu_shutdown: implement default weak function</title>
<updated>2023-08-09T02:34:25Z</updated>
<author>
<name>Meco Man</name>
<email>920369182@qq.com</email>
</author>
<published>2023-08-07T16:42:10Z</published>
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<id>urn:sha1:c6a2f5b7bdee378cc868ee9284e760ebbdf635f0</id>
<content type='text'>
and remvoe duplicated default functions in each cpu/bsp level
</content>
</entry>
<entry>
<title>[risc-v][libcpu] 删去无用局部变量 (#7634)</title>
<updated>2023-06-07T21:04:12Z</updated>
<author>
<name>Liu,Yuan</name>
<email>89723088+linshire@users.noreply.github.com</email>
</author>
<published>2023-06-07T21:04:12Z</published>
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<id>urn:sha1:1d8165851b7fef9a4ec4903154b5b7234fe141b5</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[atomic] add stdc atomic detection. (#7536)</title>
<updated>2023-05-20T15:41:29Z</updated>
<author>
<name>Bernard Xiong</name>
<email>bernard.xiong@gmail.com</email>
</author>
<published>2023-05-20T15:41:29Z</published>
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<id>urn:sha1:4b4c3c85f2ac82f12d5527ef1a6794b2189a9eee</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[utest][atomic]添加返回值测试 (#7124)</title>
<updated>2023-03-30T03:06:21Z</updated>
<author>
<name>Yaochenger</name>
<email>75192526+Yaochenger@users.noreply.github.com</email>
</author>
<published>2023-03-30T03:06:21Z</published>
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<id>urn:sha1:38eb3fc40f817ea1dce5223a9bac0d2d3b578bd2</id>
<content type='text'>
* [utest][atomic]添加返回值测试
</content>
</entry>
<entry>
<title>[bsp]fix esp32_c3 compile error (#7107)</title>
<updated>2023-03-29T11:01:26Z</updated>
<author>
<name>flyingcys</name>
<email>flyingcys@163.com</email>
</author>
<published>2023-03-29T11:01:26Z</published>
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<id>urn:sha1:0cf3bcf49506ee4a8c5444284b0c9dd5afbf2df3</id>
<content type='text'>
* fix rt_hw_interrupt_install return value

* add __rt_rvstack</content>
</entry>
<entry>
<title>[atomic]添加arm与risc-v下的常用原子操作函数 (#7053)</title>
<updated>2023-03-23T12:06:50Z</updated>
<author>
<name>Yaochenger</name>
<email>75192526+Yaochenger@users.noreply.github.com</email>
</author>
<published>2023-03-23T12:06:50Z</published>
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<id>urn:sha1:de4f23748212dbba7d0250fdac3ae583e74fcbed</id>
<content type='text'>
* Update Kconfig
* Update trap_gcc.S
* Update bsp/hifive1/drivers/SConscript

Co-authored-by: Man, Jianting (Meco) &lt;920369182@qq.com&gt;
* Update SConscript
* [atomic]提交一份arm与risc-v架构下的常用原子操作函数
* 修改变量类型
* 更新rtatomic.h与atomic_port.c
* 更新rt-thread\libcpu\arm\common\atomic_port.c
* 更新include/rtatomic.h与libcpu/arm/common/SConscript
* 更新include/rtatomic.h
* 修正格式与Kconfig
* 修正格式与文件结构

* 规范文件格式与文件重命名
* 添加测试用例与CI
* 添加函数声明
* 修改virt64/SConscript 添加atomic_riscv.c
  * 1.规范代码风格
  * 2.添加RISC-V64原子指令支持 解决在RV64下编译器将32-bit运算结果扩展为64-bit 导致判断错误
* 添加C11标准库原子操作测试

---------

Co-authored-by: Man, Jianting (Meco) &lt;920369182@qq.com&gt;</content>
</entry>
<entry>
<title>[bsp] add bl808 lp core (#7069)</title>
<updated>2023-03-19T15:16:12Z</updated>
<author>
<name>flyingcys</name>
<email>flyingcys@163.com</email>
</author>
<published>2023-03-19T15:16:12Z</published>
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<id>urn:sha1:a538b268588ae668ff897c3719b6a7eef9ac8c0a</id>
<content type='text'>
* Add riscv_32e support

* add bl808 lp core

* update README.md</content>
</entry>
<entry>
<title>[libcpu][riscv]整合libcpu/riscv中的移植文件 提供一份公共代码于common (#6941)</title>
<updated>2023-03-01T06:32:43Z</updated>
<author>
<name>Yaochenger</name>
<email>75192526+Yaochenger@users.noreply.github.com</email>
</author>
<published>2023-03-01T06:32:43Z</published>
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<id>urn:sha1:b9e4fcfc6878aa05cca277ea3557299e59207965</id>
<content type='text'>
整合libcpu/riscv中的移植文件 提供一份公共代码于common

在提交本pr时，除hpmicro的内核，rv32内核bsp已完成去除大部分的冗余，大部分代码采用common中的实现。本pr的作用是进一步统一common中的文件，从而提供一份公用代码，新移植的RV32内核的BSP可以全部使用common代码。

- 在common中提供一份公用文件：interrupt_gcc.S
- 修改原有的文件，将原有的中断中上下文切换代码替换为interrupt_gcc.S
- 基于上述修改，修改仓库中risc-v内核的BSP与移植相关的部分 (主要包含中断入口函数 中断栈等)
- 在common中提供一份公用文件：trap_common.c；提供统一中断入口函数，中断入口函数初始化，中断入口注册等函数，并完善异常时的信息输出

- 在common中提供一份公用文件：rt_hw_stack_frame.h；将栈帧结构体剥离，供用户使用

- 在上述工作完成后，在上述工作的基础上测试仓库中risc-v内核的BSP

- 完善函数中的命名，完善中断栈的获取

- 提供一份详细的基于现有common文件的移植指南

  #### 在什么测试环境下测试通过 

- 1.CH32V307V-R1-R0
- 2.CH32V208W-R0-1V4
- 3.HPM6750EVKMINI
- 4.GD32VF103V-EVAL
- 5.qemu(CORE-V-MCU )

&gt; 与上述开发板使用同样芯片的BSP均测试通过

在CH32V307V-R1-R0与HPM6750EVKMINI上基于现有移植文件进行多线程复杂场景下的长时间测试，测试过程系统运行正常。</content>
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