rt-thread.git/libcpu/risc-v/common, branch v5.2.0-betaUnnamed repository; edit this file 'description' to name the repository.http://cgit.235523.xyz/rt-thread.git/atom/libcpu/risc-v/common?h=v5.2.0-beta2025-03-10T14:48:27Z[libcpu][riscv] add a doc for wch saving the irq stack as stack-512 (#10063)2025-03-10T14:48:27ZKai60053077+kaidegit@users.noreply.github.com2025-03-03T15:13:11Zurn:sha1:35b886726cc13039029608e3c1aee6a6f8c094d3libcpu: riscv: common: fixed build warnings2025-01-30T01:28:38ZChen Wangunicorn_wang@outlook.com2025-01-27T02:58:05Zurn:sha1:2dfbae28532303526f6bf4b60a54794c845d444a
When building bsp/cvitek/c906_little, compiler warns:
```
.../rt-thread/libcpu/risc-v/common/trap_common.c:
In function 'rt_hw_interrupt_install':
.../rt-thread/libcpu/risc-v/common/trap_common.c:50:11:
warning: unused variable 'user_param' [-Wunused-variable]
50 | void *user_param = param;
| ^~~~~~~~~~
.../rt-thread/libcpu/risc-v/common/trap_common.c:
In function 'rt_rv32_system_irq_handler':
.../rt-thread/libcpu/risc-v/common/trap_common.c:77:25:
warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
77 | s_stack_frame = (rt_hw_stack_frame_t *)mscratch;
| ^
```
Fixed these warnings as per indication from gcc.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
[libcpu][risc-v]add README for RV642024-10-08T21:56:55Zzhangjing0303161287203+zhangjing0303@users.noreply.github.com2024-10-08T21:56:55Zurn:sha1:bf8f7b04b5b32faf37a7a2ea04fcf57c27039b5c[bsp][ch32] add eth driver2024-08-01T09:31:52ZYaochenger1516081466@qq.com2024-07-25T09:40:56Zurn:sha1:a4a59532567766a250ae6c51ce5e1a465a05027aBugfix/fix weak handle trap in riscv common crash rv64 trap handling (#9189)2024-07-15T09:51:32ZFan Yang93824713+helloeagleyang@users.noreply.github.com2024-07-15T09:51:32Zurn:sha1:96ba787e252c38abe08f039c052a4be378dfa42c
* [bsp][hpmicro] add weak handle_trap implementation
- added weak handle_trap implementation
Signed-off-by: Fan YANG <fan.yang@hpmicro.com>
* [libcpu][risc-v][common] remove weak handle_trap function
- removed weak handle_trap function from trap_common.c
Signed-off-by: Fan YANG <fan.yang@hpmicro.com>
---------
Signed-off-by: Fan YANG <fan.yang@hpmicro.com>Fix compiling eror in hpmicro bsp (#8889)2024-04-30T12:11:47ZFan Yang93824713+helloeagleyang@users.noreply.github.com2024-04-30T12:11:47Zurn:sha1:c21ba6985d5a9d6f6926799ada4faa92c20cb8a0
- added 'DEVICE' to rtconfig.py
- fixed compiling error cuased by change in interrupt_gcc.S
Signed-off-by: Fan YANG <fan.yang@hpmicro.com>[libcpu][SConscript]规范group名为libcpu2024-02-20T00:39:05ZMeco Man920369182@qq.com2024-02-19T19:33:47Zurn:sha1:6d4503363a352c72148bc91da3026f0db096f119add libcpu/risc-v/rv64 (#8511)2024-01-28T05:39:39Zflyingcysflyingcys@163.com2024-01-28T05:39:39Zurn:sha1:3f41bd95d10bf02de049290434af587c5586fde5[libcpu][risc-v][common] Fix application crash on risc-v soc if FPU is2023-08-12T01:20:28ZFan YANGfan.yang@hpmicro.com2023-08-11T13:05:52Zurn:sha1:5308cc47161d8e2f9fdb680738e023ef16af1e2b
enabled
- Defined ARCH_RISCV_FPU once the __riscv_flen macro was detected
Signed-off-by: Fan YANG <fan.yang@hpmicro.com>
[libcpu][risc-v][common] Avoid using t0 before being saved2023-08-09T05:07:11ZFan YANGfan.yang@hpmicro.com2023-08-09T02:51:32Zurn:sha1:5ac509b6d031b29e2d95c52fc179771e62664378
- Fixed the issue that t0 was modified unexpectedly before being saved
Signed-off-by: Fan YANG <fan.yang@hpmicro.com>