rt-thread.git/libcpu/risc-v/e310/context_gcc.S, branch v3.1.1 Unnamed repository; edit this file 'description' to name the repository. http://cgit.235523.xyz/rt-thread.git/atom/libcpu/risc-v/e310/context_gcc.S?h=v3.1.1 2018-05-31T06:53:26Z [libcpu] add risc-v e310 porting 2018-05-31T06:53:26Z liang yongxiang tanekliang@gmail.com 2018-05-31T05:01:38Z urn:sha1:32c5b2515f29d1b3a7969da294de015547d69646 [libcpu] remove libcpu/risc-v 2018-05-29T04:59:13Z liang yongxiang tanekliang@gmail.com 2018-05-29T04:50:07Z urn:sha1:5faae3350cddbf406d2d9d257e7727ddd80ea69b fix bug in context_gcc.s and start_gcc.s: 2017-07-31T02:59:59Z zhangjun 2281979437@qq.com 2017-07-31T02:59:59Z urn:sha1:a5305c05df3e97cd60c621bec87926765ba31228 save mie into stack msh running normaly fix bug in rt_hw_context_switch_interrupt_do 2017-07-30T11:46:28Z zhangjun 2281979437@qq.com 2017-07-30T11:46:28Z urn:sha1:b032dff1616fe64a4dfec63e593f0fac634ef3ab save sp to old thread clear rt_thread_switch_interrupt_flag always enable interrupt after rt_hw_context_switch judeg the type of interrupt in trap_entry, then call handler(Machine timer interrupt of Machine external interrupt) 修改： ../../libcpu/risc-v/e310/context_gcc.S 2017-07-30T07:34:32Z zhangjun 2281979437@qq.com 2017-07-30T07:34:32Z urn:sha1:2d56a27c20d430f678a77e48f1d00591f4fc4c8b enable interrupt after return form rt_hw_context_switch fix trap_entry 2017-07-29T07:37:20Z zhangjun 2281979437@qq.com 2017-07-29T07:37:20Z urn:sha1:3c51848d33d2c13d0029f3e796af9f78a882eac3 modified: ../../libcpu/risc-v/e310/context_gcc.S 2017-07-26T08:27:54Z zhangjun 2281979437@qq.com 2017-07-26T08:27:54Z urn:sha1:b80f83f360261156af3d502db659e9c53a6222a0 fix open timer intrrupt remove "csrrc a5, mstatus, MSTATUS_MIE" in rt_hw_interrupt_enable(); 2017-07-26T08:07:01Z zhangjun 2281979437@qq.com 2017-07-26T08:07:01Z urn:sha1:98a6896cfa5b577503139363ffc141418d55412f it will lead to interrupt again in interrupt deleted: rtthread.s /*just for debug*/ 2017-07-17T08:55:33Z zhangjun 2281979437@qq.com 2017-07-17T08:55:33Z urn:sha1:b334347a244d95007738622ce2daac61694cb314 modified: ../../libcpu/risc-v/e310/context_gcc.S change ret to mret and switch to new task with mepc add context_gcc.s 2017-07-17T07:44:00Z zhangjun 2281979437@qq.com 2017-07-17T07:44:00Z urn:sha1:e01455155ab5a564eddd467b02a0226b3fa5ea7d